How to code nested FSM states in VHDL

[omara007]

Nested FSM states

Hi folks

What is the best way to code nested FSM states in VHDL ? .. i.e. when we have a parent state (say X) that has more than one child states (say Y,Z, etc) that are all encapsulated inside it.

 

[bapodradhairyab]

for that you need to pass one signal from state X that is enable of module that is called in side them main FSM, this submodule contains FSM that have the child states of X for say Y,Z etc...

Now from that submoudle pass one output signal that indicate completion of particular task and it is also indication for state change in main state machine that contains state X...

Simplest way is this to do so...

pass signal start for child states receive complete acknowledge from submodule

 

[omara007]

what if the parent state is encapsulating the child states .. i.e. like having a parent sphere that has smaller child spheres inside it ..

 

[FvM]

The specification of hierarchical FSM behaviour isn't really a VHDL problem in my opinion. It just hast to be done unequivocally.

If you have the specification, you can directly write down the VHDL description, FSM is behavioural VHDL code anyway.

You have the choice of either coding it with hierarchical states or in a flattened representation. If you specified the behaviour
correctly, both should be functional equivalent.