premcupid
Newbie level 3
simulink co simulate
i have attached my simulink model here...(renamed file extension from .doc to .pdf)
upper part is for checking functionality using floating point filters. after achieving it below i have created a ''equivalent fixed point subsytem''
so i have to generate HDL code for that ''equivalent fixed point subsytem'' and co-simulate it.
but HDL coder not highlighted(non functional).
i came to know that, to generate HDL for a model.
it shud be clear of all scopes or wave generators and also should only have required blocks and i/p and o/p ports.
so now i copied all the elements from ''equvalent fixed point subsytem'' into a new file "CopiedSubSystem"
saved it and opened it, opend port "In1" properties ,in signal attributes i gave sample time as 1/6000(otherwise u will get error),updated diagram, and now HDL coder can be seen..and i generated vhdl and verilog code...
when i tried to synthesize the generated code in xilinx ISE it fails saying "line 27: Signal <In1> of type real is not supported."
it is beacause we are inheriting properties(-1) from previous stages like quantizer. and quantizer o/p signal format is real(double).
now i reopened "CopiedSubSystem'' and In1 properties,in signal attributes i defined data type as fixdt(1,16,0). and updated diagram, and generated vhdl or verilog. now the code is synthesizable without any errors(but few warnings), i could also see rtl, techonology schematics.
now plz guide me to co-simulate the generated HDL code..
what are the ways?
can xilinx chip scope be used? if not what shud be used?
some how I need wave from matlab simulink to get into verilog code and o/p seen again in matlab scope.
my deadline is already over(1month late). its bit urgent. plz
i have attached my simulink model here...(renamed file extension from .doc to .pdf)
upper part is for checking functionality using floating point filters. after achieving it below i have created a ''equivalent fixed point subsytem''
so i have to generate HDL code for that ''equivalent fixed point subsytem'' and co-simulate it.
but HDL coder not highlighted(non functional).
i came to know that, to generate HDL for a model.
it shud be clear of all scopes or wave generators and also should only have required blocks and i/p and o/p ports.
so now i copied all the elements from ''equvalent fixed point subsytem'' into a new file "CopiedSubSystem"
saved it and opened it, opend port "In1" properties ,in signal attributes i gave sample time as 1/6000(otherwise u will get error),updated diagram, and now HDL coder can be seen..and i generated vhdl and verilog code...
when i tried to synthesize the generated code in xilinx ISE it fails saying "line 27: Signal <In1> of type real is not supported."
it is beacause we are inheriting properties(-1) from previous stages like quantizer. and quantizer o/p signal format is real(double).
now i reopened "CopiedSubSystem'' and In1 properties,in signal attributes i defined data type as fixdt(1,16,0). and updated diagram, and generated vhdl or verilog. now the code is synthesizable without any errors(but few warnings), i could also see rtl, techonology schematics.
now plz guide me to co-simulate the generated HDL code..
what are the ways?
can xilinx chip scope be used? if not what shud be used?
some how I need wave from matlab simulink to get into verilog code and o/p seen again in matlab scope.
my deadline is already over(1month late). its bit urgent. plz
