How to Choose Best 650 V , 60A GaN Transistors for Switching Losses ?

[Ali Z]

Hi ,
I will calculate GaN transistors switching losses in Dc DC converter Systems.
The formula is , Psw= Vds*Id*fsw*((Ton+Toff)/2) .
Vds and Id are drain-source voltage and drain current of the device at OFF and ON intervals respectively.
fsw switching frequency and Ton is switching time during ON transition, and Toff is switching time during OFF transition.
Ton and Toff times important , how much lower its best to get less switching loss. So how can I undertand from datasheet which GaN transistor or Fet or mosfet is best for this ?

 

[cupoftea]

Full switching loss calc is as per "Design And Application Guide For High Speed MOSFET Gate Drive Circuits" document by Laszlo Balogh.

Also, what topology is it?.....the switching losses will depend on eg....PFC FET with non SiC diode (rev rec extra sw loss)...also, PSFB and LLC dont have much ON switching loss.

But yes.....you also dont give the driver max current capability...because it is that that must charge up Cgs to Vgsth at first...and then charging up Cgs in the interval just after it reaches the lowest point of vgsth......because vgsth is not just one voltage...the vgsth is a slowly rising plateau......to make things that bit more interesting for us....and you should calc this out.........then you need to use the transconductance to calculate the vgs where its able to carry the full drain current.

There is also the "mad_hot" interval where eg in boost converter swithing ON...there is a "mad hot" interval where the full drain "valley" inductor current flows through the FET with full VDS(OFF) across it!.....you should calc this too......using i=cdv/dt etc etc

See Laszlo Balogh...

http://danielscastle.com/Design%20And%20Application%20Guide%20For%20High%20Speed%20MOSFET%20Gate%20Drive%20Circuits%20-%20Laszlo%20Balogh.pdf

 

[FvM]

To utilize the switching speed advantage of GaN FETs, your circuit layout must be designed to handle it. Otherwise there's no advantage for GaN.

 

[Ali Z]

I am using DC DC converter ( Multi device interleaved boost converter) . it will boost 27kW battery which is 201.6 volt Dc input voltage to the 650 V dc . So the switching process will be with GaN transistors . so I have to work 60A Gan transistors with 650 V.
Actually Ton and Toff switching time is getting after simulation. But How can I understand from datasheet Ton and Toff will be short time ? So How i will choose best GaN for this process.
According to this formula Psw= Vds*Id*fsw*((Ton+Toff)/2) which parameters should I look at in the datasheet
?
when I compare with other datasheets which parameter is important to be low ?

 

[cupoftea]

Here is some good stuff

Is this a synchronous design with two gan fets per booster?
Or is it a diode_booster?....if so, then the diode must be SiC..otherwise no point in gan.

I think to get from 20V to 650V with a boost, you would need it to be a dual. or triple boost.

 

[Easy peasy]

You should buy a demo board to see how the layout and heatsinking must be for these devices - also mounting / soldering can be very tricky if you have not done similar before ...

 

[mtwieg]

I am using DC DC converter ( Multi device interleaved boost converter) . it will boost 27kW battery which is 201.6 volt Dc input voltage to the 650 V dc . So the switching process will be with GaN transistors . so I have to work 60A Gan transistors with 650 V.

If your output voltage is 650V, then a 650V GaN FET isn't sufficient. The only available GaN FET I'm aware of with VDDS>650V is from Transphorm, but it's in a TO-220 package, which IMO negates a lot of the benefits of GaN (but I've never actually tried them).

Why are you considering GaN FETs for this application? SiC might be a much better option.