How to check the Technology in Synopsys DC?

[Sparc]

Hi All, I have landed up in some querries with DC and hope that you guys can help me out in finding the answers. I have tried the manuals & google but wasn't that lucky.
If i am using target_library class.db or anyother .db.
1.) Is there any method which can tell me what technology i am working on?
2.) Will it effect the WLM models i want to use?
3.) Are WLMs technology dependent? and How to select them?

Thanks in advance..

 

[aravind]

1.when u report library u can see what technology ur following or report timing any report will give this information.
u have to use WL models.
otherwise it will take the default values of WLM.
u have to tell the DC to that this type (10X10" or 20X 20") in scripts.

 

[eda_wiz]

3.) Are WLMs technology dependent? and How to select them?

Yes WLMs are process dependant. WLMs are RC estimates of interconnects based on statistics. They are selected based on the area of the block you are synthesising. As area increases interconnect RC increases so higher WLM is chosen.

 

[jcchan]

When Synthesizer will use the target lib for cell mapping.

 

[dr.farnsworth]

after you use compile command it maps the design with library cells..

regards,
Dr.farnsworth

 

[5life]

I think the command "report_lib" is ok

 

[sr66]

1) In DC do the following:
list_libs
Based on output above, locate the library name, should be on the same line as your library file name. Then do:
report_lib lib_name (example: report_lib class)
This will give some basic info on the procees used. For detail process information. you should refer to the library data book.

2) Yes. You should use the wire load models that are available in your target_lib (or in some cases from your link libraries). If you are synthesizing a design for say, TSMC 0.25u, then you must use the wire load models in the library provided by TSMC for the 0.25u process. You should not use a wire load model from some other process or foundary.

3) WLM are technology dependent. However the accuracy drops for 0.18u and below. Generally there are two ways to use WLM:
a) Manually - you select A wire load from the list available from your library. Generally WLM are developed based on area. What we normally do is, take a design, do a quick synthesis (no constraints), just get the gate-count (area), and based on that, we choose the WLM for our actual run.
b) Let DC choose. If your lib have the auto WLM table, DC will choose one for you.

Bottom line: do some research on your WLM to see if its optimistic or pessimistic. If its optimistic - just overconstrain your design, about 10% to account for any errors.

 

[semi_jl]

use the command:read_lib, or :link_library

 

[yuenkit]

type list_lib, get the library name first (not the library filename), followed by the report_lib