How to check the module delay.

[EDA_hg81]

How can I check the signal delay of the module written by VHDL if I don’t run simulation?

Thanks.

 

[FvM]

The timing analysis of your synthesis tool is supposed to check it against existing timing constraints. And to report the results.

 

[EDA_hg81]

One question:

If the “if () then” is going to generate one clock delay inside process?

If it is true, I can count how many “if() then” is nested inside process for deciding the output data delay.

Thanks.

 

[dcreddy1980]

As FVM said, you have to run STA if you dont want to run your simulations.

If you have a RTL design, try to represent in to hardware .i.e how it looks like by using standard cells and try to compute the delay by looking up into the library file. But this is unrealistic since you have to know how much is the load on all the signals and u have to add certain wire delay as well.This method is for approximation only.

u want an accurate delay, u have to go for STA. any other comments from others are welcome