library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity music is
port (
clk : in std_logic;
q : out std_logic);
end music;
architecture music_behave of music is
signal tone : std_logic_vector(22 downto 0) := "0000000000000000000000";
signal ramp : std_logic_vector(6 downto 0);
signal clkdivider : std_logic_vector(14 downto 0);
signal counter : std_logic_vector(14 downto 0);
begin -- music_behave
ramp <= tone(21 downto 15) xor ((not tone(22)) & (not tone(22)) & (not tone(22))
&(not tone(22)) &(not tone(22)) &(not tone(22)) &(not tone(22)));
clkdivider <= "01" & ramp & "000000";
process (clk)
variable q_tmp : std_logic := '0';
begin -- process
if clk'event and clk = '1' then -- rising clock edge
tone <= tone + '1';
if (counter = 0) then
counter <= clkdivider;
q_tmp := not q_tmp;
else
counter <= counter - 1;
end if;
end if;
q <= q_tmp;
end process;
end music_behave;