Eragon777
Newbie level 1
Hi,
I am simulating my postgraduate PCB design project using Hyperlynx SI tool. I am testing on PCIe traces of my design. I did my design using Altium and I exported to Hyperlynx file to do the simulation. I have a issue in TX differential pair of the design. It did not pass the simulation. So I need to change the trace width and spacing of the TX differential pair traces to overcome this problem.
But I cannot change the trace width and spacing of Differential pairs using Hyperlynx SI tool. Is there any way to do that?
If that is so can you tell me steps to do that?
Thanks
I am simulating my postgraduate PCB design project using Hyperlynx SI tool. I am testing on PCIe traces of my design. I did my design using Altium and I exported to Hyperlynx file to do the simulation. I have a issue in TX differential pair of the design. It did not pass the simulation. So I need to change the trace width and spacing of the TX differential pair traces to overcome this problem.
But I cannot change the trace width and spacing of Differential pairs using Hyperlynx SI tool. Is there any way to do that?
If that is so can you tell me steps to do that?
Thanks