calculating voltage gain
Thanks for the explanation.
Yes, the currents in the M7 and M8 do change in the complementary mode when there is AC signal added to the input stage. This is interesting, and i am just curious to know how this circuit structure make this. How to design the W/L size of M7 and M8?
Another interesting thing is that when VA decrease (output PMOS pull current from Vdd), the VB is kept to a minimum voltage (about 700mV), and when VB increase ( output NMOS drive current to GND), the VA is kept to a maximum voltage (about 4.1V, vdd=5V). What 's the purpose?
best regards/