Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to calculate the number of Slices needed for a design?

Not open for further replies.


Advanced Member level 4
Aug 19, 2005
Reaction score
Trophy points
Activity points
doubt about Slices

HI all
I just cost 16 FlipFlops/Latches for my design why the report indicating me it spent 9 Slices for the design ,who can tell me how to calculate it ( i just think it will cost me 8 Slices)

Cell Usage :
# FlipFlops/Latches : 16
# FDR : 16

# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 33
# IBUF : 17
# OBUF : 16
Device utilization summary:
Selected Device : 2v6000ff1152-5
Number of Slices: 9 out of 33792 0%
Number of Slice Flip Flops: 16 out of 67584 0%
Number of bonded IOBs: 33 out of 824 4%
Number of GCLKs: 1 out of 16 6%

thank you in advance

doubt about Slices

Hi Matrix,
each slice has got 2 LUTs, and the output of each LUTs can be registerd on the the flipflops inside the Slices.And they are called "Slice Flipflops". As ur design needs 16 flipflops, it is implemented using these Slice flipflops. And so only the report says that "it uses 9 slices". you can see the slices used using the P&R editor(FPGA Editor).

Cheers !!!

Re: doubt about Slices

You also have to measure the amount of logic that you ar using.

Doyou use only 16FF? Or there is some additional combinational logic?

Each slice has a limited capacity for implementing logic.

As Renjith said, you can use the P&R editor to see what's happening, and what are those 9 silces used for.

doubt about Slices

Maybe the router put some combinatorial logic into the 9th slice. Or maybe it put a few flops into separate slices instead of packing all of them two per slice. The statistics report counts a partially-used slice as one slice. Your chip has plenty of unused space, so the place-and-route sometimes spreads things out. That's harmless.

Try running FPGA Editor to see the routing details. You can zoom in to inspect the individual slices and routes.

Not open for further replies.

Part and Inventory Search

Welcome to