How to calculate the depth of FIFO in this case?

[zhangljz]

Hi all,

In my case, there are about 70 LVDS transmitters, and between the transmitter and data source there should be a FIFO. But the throughput of the data source is higher than LVDS throughput, the former is about 1.4Gbps, the latter is about 1.1Gbps. So generally, no matter what the depth is, it will overflow. In this case, how to decide the depth of FIFO?

Besides, for the FIFO memory, which kind of memory is better, register file, RAM or filp-flops arrays ?

Thank you.

 

[sharath666]

You need to have the data rates the same on both sides of the FIFO. Write can never be faster than read (which is your case). So using a FIFO here might not be the best approach.

 

[zhangljz]

Thank you. But the read and write operations are in different clock domains. If no FIFO, I have no idea how to do it. Can you give me some suggestions?

 

[sharath666]

The read and write clocks being different is ok. This is a valid scenario. But what you need to ensure is that the effective data rates are the same(on both sides). You cannot pump in more data to a block than it can handle which is the case here. One possibility is that you can increase the data width on the read side such that the data rates balance.

 

[littlebu]

I am not trying to answer your question, and just want to discuss why you ignore overflow? Is any requirement of stream stability? For example, it is acceptable FIFO overflow every 3s (!?). Is that true? Otherwise, it is not make sense to me that in/out ports of FIFO have different data rate..