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how to calculate ratio fo cmos transistors

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ikru26

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how to fix metal widths in cmos layouts

1) According to Clein, what has been one of the main reasons why CAD
tools have failed to be successful among IC layout engineers?

2) With respect to CAD tools, what are some of the advantanges and
disadvantages to being a small IC design house?

3) What is an IC design flow? Why do IC design teams operate within
the constraints of design flows?

4) Why are PMOS transistor networks generally used to produce high (i.e. 1)
signals, while NMOS networks are used to product low (0) signals?

5) On IC schematics, transistors are usually labeled with one, or sometimes
two numbers. What do each of those numbers mean?

6) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)
usually limited to four?

7) What is meant by static and dynamic power with respect to the operation
of a CMOS gate? Why do CMOS gates dissipate close to zero static power?
Why is the static power not exactly zero?

8) What is a transmission gate, and what is it used for typically? Why
are transmission gates made with both PMOS and NMOS transistors?

9) What are the major factors that determine the speed that a logic signal
propagates from the input of one gate to the input of the next driven gate
in the signal's path?

10) What are some of the major techniques that are usually considered when
one wants to speed up the propagation speed of a signal?

11) What is the difference between a mask layer and a drawn layer in an
IC layout? Why do layout designers usually only specify drawn layers?

12) In an IC layout, what is a polygon and what is a path? What are the
advantages and disadvantages of each?

13) What is the difference between a contact and a via? What is a "stacked"
via process?

14) Why is it that NMOS transistors can be created directly in a P-type
substrate, whereas PMOS transistors must be created in an N-type well?

15) Why must transistors be provided with "bulk" connections? What voltage
levels are connected to a p-type substrate and an n-type well through these
connections, and why?

16) What are process design rules? What is their major purpose? How are
design rules created?

17) What are width rules, space rules, and overlap rules?

18) What is a "vertical connection diagram"? What is it used for?

19) The routing strategies for the power grid and global signals are usually
defined at the start of planning a new chip floorplan. Why?

20) What are the major advantages of hierarchical IC design?

21) Define what is meant by the terms design rules checking, layout versus
schematic, and electrical rules check? Are all three procedures required
in every chip design?

22) What is meant by the term "porosity"? Why is it desirable for a cell
or macro to have high porosity?

23) What are the main differences in priorities between microprocessor design,
ASIC design, and memory design? How are those differences reflected in
the corresponding design flows?

24) What is an "application-specific memory", according to Clein? What are
some specific examples of this part type?

25) What is the difference between a soft IP block (soft core) and a hard
IP block (hard core)?

26) In ASIC design, what are the main advantages of expressing the design
using a hardware description language, such as VHDL or Verilog?

27) Why are memory layouts designed primarily from the bottom up, instead of
from the top down, like other ICs?

28) With respect to a memory layout, what is meant by "array efficiency"?

29) What is "pitch-limited layout"? What are some of the major circuits
in a memory layout that must meet pitch-limited constraints?

30) What are some of the typical kinds of cells that one would expect to
find in a library of standard cells?

31) The layout of standard cells is constrained to simplify the job of
place & route tools. Give several examples of these constraints.

32) Why did older cell libraries include so-called feedthrough cells? Why
are such cells no longer required in cell libraries for modern processes?

33) What is electromigration? How does electromigration affect the design of
a standard cell based design?

34) What is a gate array? Why are main advantages of using gate arrays to
implement an IC? What are some of the main disadvantages, with respect to
custom design or standard cell based design?

35) Why might one want to use some gate array based design inside an otherwise
custom IC design, according to Clein's experience?

36) What are some of the major similarities and differences of standard cells
and datapath cells?

37) How is the problem of driving a clock node different from that of designing
a regular signal node? What are the key goals when laying out a clock node?

38) What is a "pad frame"? What are "staggered" pads?

39) Why are 90 degree corners usually avoided in the layout of pad cells?

40) In the layout of output pad driver transistors, why is the gate length
often lengthened at both ends of the gate?

41) Why is the pad ring provided with power supply connections that are
separate from those of the core design?

42) What are so-called friendly cells in a DRAM core design? Why and where
these cells included in a memory design?

43) Why are metal straps used along with polysilicon wordlines in memory designs?

44) Why are wordline driver circuits very long and narrow?

45) Describe some of the alignment keys that are included in IC layouts.

46) Why is the power supply interconnect layout layout planned out before
other elements? Similarly, why are busses, differential signals, and shielded
signals routed before other general signals?

47) What are the root and resistance styles of power supply layout?

48) What are some of the main reasons why clock skew minimization is such a
major design challenge?

49) What are the major advantages and disadvantages of using a single clock
tree conductor driven by one big buffer?

50) In ASIC design flows, why are clock trees inserted after the logic cells
have been placed? In such clock trees, how is clock skew minimized at the
leaves of the tree?

51) What is a routing channel? Why are routing channels used in IC layouts?

52) Why is the estimated area for routing channels increased by 10% during
early stages of layout planning?

53) When routing a signal interconnect, why is it desirable to minimize
layer changes through vias?

54) Interconnect resistance is usually minimized in IC layouts. Give at least
four situations where a deliberably large, but controlled, resistance is
usually required?

55) Why should minimum-width paths be avoided in the design of deliberate
resistances?

56) Usually one wishes to minimize the capacitance of electrical nodes in an
IC design. Give four examples of circuits where one would wish a larger,
but controlled, capacitance at a node?

57) The capacitance on a node is the sum of several components. What is meant
by fringe capacitance? How does reducing the width of a conductor affect the
fringe capacitance?

58) How can the parasitic capacitance between two signal nodes possibly cause
the signal transition on one of the nodes to be unexpectedly sped up?

59) How can a layout designer help ensure that the propagation delay along two
conductors is very similar?

60) List four situations where it may be desirable to have 45 degree corners
in the interconnect.

61) Explain what is meant by electromigration. What are some possible
consequences of unexpectedly high electromigration? How is electromigration
controlled in IC layout design?

62) Why are wide metal conductors, such as those in the power rings, provided
with slits? What constraints must be followed when positioning these slits?

63) When placing multiple vias to connect two metal conductors, why is it better
to space the vias far apart from each other?

64) Why would a DRAM layout be verified against two or more different sets of
design rules?

65) What is the antenna effect, and how can it cause problems in an IC design?
What are two layout techniques that can be used to reduce vulnerability to the
antenna effect?

66) What is the purpose of minimum area design rules?

67) What is the purpose of end overlap rules?

68) What is the phenomenon of latch-up? Why is it a serious concern in CMOS
layout design?

69) Describe six different layout strategies that are commonly used to minimize
the possibility of latch-up.

70) Why is it wise to plan designs to make it easier to change details later?

71) What is meant by metal strap programmability and via programmability?
Give one example where each techniques is commonly used.

72) What is the difference between test pads and probe pads?

73) Dan Clein advocates the use of contact and via cells, which is not a
common design practice. What are his reasons?

74) In which situation should one avoid using the minimum allowed feature sizes
allowed by the design rules?

75) What fundamental factors limits the speed with which detected design errors
can be corrected?

76) When floorplanning a chip at the start of the IC layout process, what are
the main goals in deciding how to arrange the major blocks in the design?

77) How is block floorplanning different from chip floorplanning?

78) What is a silicon compiler? How is it different from a tiler?

79) What is the difference between a channel router and a maze router?
Which type of router will tend to produce higher utilization factors?

80) What is a chip assembly tool? What kind of routing should a chip assembly
tool provide to have maximum flexibility?

81) At IBM, it has been found to be advantageous to sacrifice performance when
migrating a chip design in one process into a second process. Process migration
is facilitated by the use of "migratable design rules". What is the major
benefit that can be obtained by such rules to offset the loss in potential
chip performance?

82) At IBM a design methodology has been developed that makes the layout of
standard cells very similar to that of gate array cells. What is the potential
benefit of intermixing such cells in the same chip design?

83) In its ASIC design flow, IBM uses a formal verification tool that performs
a technique called Boolean equivalence checking. What is the primary potential
benefit of using formal verification methods in design verification? What is
the conventional way of verifying the equivalence of different implementations
of the same function?

84) IBM has standardized its logic design on the use of pulse-triggered latches,
whereas the rest of the industry has tended to adopted design based on edge-
triggered flip-flops. What is the strategy that IBM has adopted to be able
to accommodate designers from other companies who wish to have ASICs fabricated
through IBM?

85) Why are terminator cells sometimes used when clock trees are inserted into
a block of placed standard cells?

86) When constructing a clock tree with distributed buffers, why is it very
desirable to keep the buffers lightly loaded near the root of the clock
distribution tree? Why can leaf nodes of the clock tree can be loaded more
heavily? Why does one aim to have a balanced clock tree?

87) What is the difference between two- and three-dimensional analysis of
interconnect capacitance.

88) Guard bands are usually built into the timing estimates employed by logic
synthesis, cell placers, and other CAD tools. What is lost when the guard
bands are relatively large? What could be gained if the timing estimates could
be made more accurate?

89) Full 3-D capacitance calculations are generally extremely timing consuming.
How can the technique of tunneling be used to make such calculations efficient
enough to use in large IC designs?

89) The output of a 3-D field solver is a charge distribution over the signal
net under consideration, and a charge distribution over the surrounding passive
nets. Generally the signal net is assumed to be at a potential of 1 volt while
the other nets are held at 0 volts. How can the signal net's self-capacitance
and coupling capacitance then be computed?

90) Moore's Law predicts a doubling in the number of transistors per chip every
two to three years. The major factor supporting Moore's Law is improvements
in lithographic resolution that permit finer features. What are the two other
major factors that Moore believes have allowed Moore's Law to hold? Even if
physical factors allow for further increases in per-chip component density,
what other factors could slow or even stop Moore's Law in practice?

91) What is meant by the term "dual damascene process"? How has the availability
of this type of process simplified the creation of multiple interconnected
metal layers?

92) In processes that have multiple layers of metal interconnect, why is it
common to make the upper wires thicker than the lower layers? (The use of
fat wires is sometimes called "reverse scaling".) In which situations would
one be willing to use reverse scaling and hence appear to throw away the
possible advantages of thinner wires?

93) What are some of the important reasons why DRAM technology has been
a pioneer for semiconductor technology advances?

94) Briefly explain what are planar DRAM cells, trench capacitor DRAM cells,
and stacked capacitor DRAM cells. Which type of cell is becoming dominant
in embedded DRAMs? Why is this so?

95) There are numerous technological challenges and additional costs with
embedded DRAM. Describe three of the main potential advantages that could
be gained with embedded DRAM. What are characteristics of an application that
could benefit from using embedded DRAM?

96) What are the three most common process solutions to providing embedded
DRAM? Discuss some of the important trade-offs that must be made when
selecting a process strategy for embedded DRAM.
 

Vamsi Mocherla

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mos layout check list

These are nice set of questions. It shall benefit us when we interview a layout engineer.
 

alittlecat

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shielding in cmos : eda forum

Dear,

It would be great if there is an answer for those question...:)

Best,
 

javi

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what is trench in cmos layout

hi

the questions are really giving new approch to the fresh layout designers .
i feel the answers for the tough questions to be discuused here.

JAVI
 

mic_huhu

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hierarchical cmos layout

maybe ,somebody can give some answer following the article
 

zahrein

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cmos layout with via

this is a long question, give me one week. I will try to answer your question.
 

alvays

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cmos ic how they work how they fail

2)advantages:good integration of tools and service cut off their time wasted on tools
disadvantages:too expensive
3)Constrain in a flow in order to integrating different part of a system and with expected results

76)power line, noise, clock tree?

89)if you can solve this, you will be one of the chairman of synopsys or cadence. This is a good question for CADers.


too tired, answer later
 

Mazi3

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40 cmos layout

are there answers to this questions? :)
 

dog1357

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nor layout cmos

4) Why are PMOS transistor networks generally used to produce high (i.e. 1)
signals, while NMOS networks are used to product low (0) signals?

This should be a question on circuit, it is because there should be a voltage difference between the source and gate of transistors to make it work, so PMOS will generate a week 0 and NMOS will generate a week 1 too.
 

kapils1982

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shielding layout cmos

Ans18vertical connection diagram illustrates the relative position, going
vertically, of all the drawn layers. Such diagrams are especially
useful in complex processses, such as DRAM processes.

Added after 3 minutes:

Electromigration is generally considered to be the result of momentum transfer from the electrons, which move in the applied electric field, to the ions which make up the lattice of the interconnect material.
 

no_mad

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dram layout

25) What is the difference between a soft IP block (soft core) and a hard
IP block (hard core)?

Answer:
Softcore
- most flexible
- exist either as a gate-netlist or RTL.

Hardcare
- best for plug and play
- less portable and less flexible.
- physical manifestations of the IP design.

A small contribution :)
 

no_mad

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pitch in cmos layout

6) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)
usually limited to four?

Answer:
To limit the height of the stack.

As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be.


:)
 

kapils1982

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Re: CMOS Layout Questions

16) What are process design rules? What is their major purpose? How are
design rules created?

The purpose of the design rules is to ensure the greatest possibility of successful fabrication.The design rules are a set of requirements and advisement that are defined by the limits of the process(ie athe stable process window)which in turn is defined by the capabilities of the individual process steps.
In general minimum design rules are defined by the resolution and alignment capabilities of the lithographic systems.

Given by the FAbs
 

svu

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CMOS Layout Questions

12) In an IC layout, what is a polygon and what is a path? What are the
advantages and disadvantages of each?
A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it's off grid with 45 degree angle. Polygon is always on-grid, unless it's a copy and flip. However, polygon is hard to edit and work with.
 

kapils1982

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Re: CMOS Layout Questions

59) How can a layout designer help ensure that the propagation delay along two
conductors is very similar?

By running the two traces side by side and making them of equal length.
 

kapils1982

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Re: CMOS Layout Questions

13) What is the difference between a contact and a via? What is a "stacked"
via process?
Via: a contact between two conductive layers.
Contact:Opening in an insulating film to allow contact to an underlying electronic device.

Added after 1 hours 3 minutes:

13) What is a "stacked via process?
The placement of vias directly over the contacts or other,lower vias is known as stacked via.
 

wholx

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CMOS Layout Questions

bon courage! this could be a good faq kit if all the experienced guys help
 

kapils1982

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Re: CMOS Layout Questions

6 What is the phenomenon of latch-up? Why is it a serious concern in CMOS
layout design?



Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS)

An SCR is a 3-terminal 4-layered p-n-p-n device that basically consists of a PNP transistor and an NPN transistor as shown in Figure 1. An SCR is 'off' during its normal state but will conduct current in one direction (from anode to cathode) once triggered at its gate, and will do so continuously as long as the current through it stays above a 'holding' level. This is easily seen in Figure 1, which shows that 'triggering' the emitter of T1 into conduction would inject current into the base of T2. This would drive T2 into conduction, which would forward bias the emitter-base junction of T1 further, causing T1 to feed more current into the base of T2. Thus, T1 and T2 would feed each other with currents that would keep both of them saturated.



Fig. 1. A parasitic thyristor that can result in latch-up

A parasitic SCR is a pseudo-SCR device that is formed by parasitic bipolar transistors in the active circuit. These parasitic bipolar transistors, in turn, result from various p-n junctions found in the circuit. Latch-up is more widely associated with CMOS circuits because CMOS structures tend to contain several parasitic bipolar transistors which, depending on their lay-out, can form a parasitic SCR by chance.

Examples of parasitic bipolar transistors that may be found in CMOS circuits are as follows: 1) vertical PNP transistors formed by a p-substrate, an n-well, and a p-source or p-drain; and 2) lateral NPN transistors formed by an n-source or n-drain, a p-substrate, and an n-well. These parasitic PNP and NPN transistors may be coupled with point-to-point stray resistances within the substrate and the wells, completing the SCR configuration in Figure 1. If such an SCR device is formed from these parasitic transistors and resistors, then latch-up can occur within the device.

Events that can trigger parasitic thyristors into latch-up condition include: excessive supply voltages, voltages at the I/O pins that exceed the supply rails by more than a diode drop, improper sequencing of multiple power supplies, and various spikes and transients. Once triggered into conduction, the amount of current flow that results would depend on current limiting factors along the current path. In cases where the current is not sufficiently limited, EOS damage such as metal burn-out can occur.

The best defense against latch-up is good product design. There are now many design-for-reliability guidelines for reducing the risk of latch-up, many of which can be as simple as putting diodes in the right places to prevent parasitic devices from turning on. Of course, preventing a device from being subjected to voltages that exceed the absolute maximum ratings is also to be observed at all times.
 

kapils1982

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Re: CMOS Layout Questions

15) Why must transistors be provided with "bulk" connections? What voltage
levels are connected to a p-type substrate and an n-type well through these
connections, and why?
Ans:To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit
 

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