matrixofdynamism
Advanced Member level 2
Suppose I connect 2 FPGAs together in a parallel bus on the same PCB. They will use simple protocol:
1. data bus - 16 bits (or may be bigger)
2. same clock
3. rd_req
4. wr_e
One FPGA shall put an address and assert rd_req then the other shall assert wr_e when data is on the bus, the bus is not bidirectiona.
Now how can I determine the maximum possible data rate for such a system? Basically, I just want to understand what factors would impact the calculation of maximum possible data rate as a function of given clock frequency. I assume that this has to do with things outside the FPGA like the PCB track length and capacitance but am not sure exactly.
1. data bus - 16 bits (or may be bigger)
2. same clock
3. rd_req
4. wr_e
One FPGA shall put an address and assert rd_req then the other shall assert wr_e when data is on the bus, the bus is not bidirectiona.
Now how can I determine the maximum possible data rate for such a system? Basically, I just want to understand what factors would impact the calculation of maximum possible data rate as a function of given clock frequency. I assume that this has to do with things outside the FPGA like the PCB track length and capacitance but am not sure exactly.