fpga instructions per second
Hi,
As far as I understand You may compile each DSP function architecture into some chip, then FPGA design tools report You maximum clock frequency achieved for Your design and then just divide the Fclk by the number of cycles needed for 1 operation. You may vary the number of pipeline stages to find out the optimal performance, this depends on the function complexity and device architecture. You may also try to make coarse manual approximations without using tools, knowing basic device timing parameters, but it is quite difficult for todays devices, synthesis tools (they may insert their own performance degradation) and function complexity.
Best Regards,
F.S.