Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to calculate fault coverage

Status
Not open for further replies.

Ameenulla

Newbie level 1
Joined
Apr 11, 2015
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
6
Hi! i wrote verilog code for low power test pattern generation and i have to apply the test pattern for benchmark circuits and calculate fault coverage how to find out fault coverage in cadence tool kindly some one help me
 

yuhiub90

Member level 2
Joined
Aug 2, 2012
Messages
52
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
Hanoi, Vietnam, Vietnam
Activity points
1,603
In general, fault coverage is calculated as the ratio of faults detected by your test patterns vs. the total number of possible faults. You need fault simulation for this. Im not familiar with Cadence tool, just give you some hints, try to research more.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top