How to calculate capacitor mismatch?

[urian]

Hi,there
I am working with a 8b pipeline ADC. People said limitation of capacitor is mismatch more than thermal noise. So I want to calculate the mismatch between Cs and Cf in the MDAC with the help of foundry process files. When I checking the documents, I find the paremeters table below with regard to capacitor, and there is no more explanation.

| Mismatch |
Area of capacitor | Mean(%) | Std.dev(%) |
50um X 50um | 0.017 | 0.023 |


I wonder what the meaning they are. What value should I use, Mean or Std?
If I use two capacitors both are 50um X 50um, then the mismatch between them is 0.017% or 0.023%?
If I use two capacitors with ratio 1:2 and have unit capacitor 50um X 50um, what is the mismatch now?
Again, If I use two capacitors with ratio 1:4 and have unit capacitor 50um X 50um, what is the mismatch now?

Thanks in advance

Regards
urian

 

[BradtheRad]

Std. dev. is probably standard deviation. It's a term used in statistical analysis.

The mean is the value halfway between the highest and lowest data. It is not necessarily the same as the average of all the data.

 

[erikl]

Std. dev. is probably standard deviation. It's a term used in statistical analysis.

Right. If mismatching is only due to process variation (not due to voltage, temperature, or layout asymmetry), a normal distribution of parameter deviations can be assumed. This means that ≈68.3% of all possible (near-by, means: as adjacent as possible) layout configurations lie within a deviation of ±1σ (sigma) = ±1 std.dev., means ≤ |±230|ppm in urian's case. If you take the 3σ value, this means ≈99.7% of all possible configurations lie below a deviation of ±3σ , or ≤ |±690|ppm in urian's case.

The mean is the value halfway between the highest and lowest data. It is not necessarily the same as the average of all the data.

I believe it's just the other way round: The mean value (or expected value) is the average of all (measured) values.

 

[urian]

Hi, according to what you said, when we consider the mismatch of capacitors, we only use the Std parameter rather than Mean? For example, if I want to estimate the capacitor area used to guarantee the gain error caused by capacitor mismatch is within acceptable range(say 0.1% mismatch will cause 1% gain error, and the gain error should be less than 0.2%), how can I do it? I know the Normal distribution, but I dont know how to relate it to the capacitor mismatch.

Regards
urian

 

[erikl]

Hi, according to what you said, when we consider the mismatch of capacitors, we only use the Std parameter rather than Mean?

Depends on your trustability (confidence level) requirement, respectively the yield you need (don't forget: the given numbers are statistic values!). If you use the std.dev. or ±1σ value, about 68% of your (to be matched) capacitor pair on all chips will have a mismatch ≦0.023% = 230ppm.

If you take the mean value number, this means that statistically 50% of your capacitor pair to be matched (i.e. 50% of all the chips which include just one pair of capacitors to be matched will contain a capacitor pair which) will lie below the corresponding 0.017% = 170ppm mismatch limit.

For example, if I want to estimate the capacitor area used to guarantee the gain error caused by capacitor mismatch is within acceptable range(say 0.1% mismatch will cause 1% gain error, and the gain error should be less than 0.2%), how can I do it? I know the Normal distribution, but I dont know how to relate it to the capacitor mismatch.

There's a proportional relationship between mismatch and gain error: if a 1% gain error is caused by 0.1% mismatch, a max. 0.2% gain error needs a max. mismatch of 0.02% = 200ppm.

What you have to consider depends on your chips' purpose: If you are evaluating a university project, you could count (with a rather low confidence level, because of the low number statistics of chips you'll receive) that about 7 of 10 caps will lie below the 230ppm = ±1σ deviation limit (or 5 of 10 below the mean value limit of 170ppm). Similar math is valid for the number of chips which fulfil the max. mismatch limit for a single device pair to be matched, stemming from a wafer resp. from a wafer lot (i.e. the (non-)mismatch yield).

If you need a lower mismatch, you'd have to enlarge the unit area: mismatch reduces inversely with the square root of the area. For example: a cross-coupled quartet of 4 unit caps (1 unit cap = 2*50µm²) decreases the mismatch of the contents of a 1σ std.dev. from 230ppm to 163ppm.

All this is only valid for just one single pair of devices to be matched (or for chips which contain only one pair of devices to be matched). If you need to calculate max. deviations valid for more than one pair of devices to be matched (or for number of chips, where all pairs of devices fulfil the deviation limits), the statistical calculations are more complicated. In a 1^st order (rather rough) estimation for low n numbers (n = number of device pairs to be matched), you may calculate with mean and the std.dev. values behaving ≈ ~√n .

 

[urian]

Hi,erikl,thank u very much for explanation!
My design is an industry project, so the yield is very important, I need the least mismatch, at least 3σ.
As you said, if I use 50um X 50um capacitor pair, only 50% of all capacitor pairs will have mismatch below 0.017%? Then if I want to get 99.7% yield I need to use 3σ rather than the Mean value to decide the cap. area? That is to say, 99.7% of all capacitor pairs will have mismatch below 0.069%?
And if I use 200um X 200um capacitor pair, the σ now is 0.00575%?
For capacitor 1:2 with unit cap. area 50um X 50um, the σ now is 0.0162%?

If you need a lower mismatch, you'd have to enlarge the unit area: mismatch reduces inversely with the square root of the area. For example: a cross-coupled quartet of 4 unit caps (1 unit cap = 2*50µm2) decreases the mismatch of the contents of a 1σ std.dev. from 230ppm to 163ppm.

Furthermore, I am little confused with this example. Do you mean the unit cap = 2*50µm2 = 50 X 50 um2 ? or = 100um2 ? If it is 50 X 50um2, that is to say, one capacitor is 50X 50um2, and the other consists of 4 50 X 50um2 , then the result I got is 230/2 = 115 ppm. What's wrong?

 

[erikl]

My design is an industry project, so the yield is very important, I need the least mismatch, at least 3σ.

That's right!

As you said, if I use 50um X 50um capacitor pair, only 50% of all capacitor pairs will have mismatch below 0.017%? Then if I want to get 99.7% yield I need to use 3σ rather than the Mean value to decide the cap. area? That is to say, 99.7% of all capacitor pairs will have mismatch below 0.069%? And if I use 200um X 200um capacitor pair, the σ now is 0.00575%?

Until here, all is correct.

For capacitor 1:2 with unit cap. area 50um X 50um, the σ now is 0.0162%?

No, I don't think so: You have to compare the mismatch of the unit cap "1" to both of the 2 other unit caps, which in both cases still is 0.023%. So for worst case (both of the "2" caps tend to mismatch into the same direction), the overall mismatch of the 1:2 (or 1:4 or 1:8) configuration still is 0.023%. Statistically it will be a bit less (because parameter mismatch tends to increase or decrease in one direction), for an industrial project, however, you always need to consider the worst case, unfortunately :-( .

Furthermore, I am little confused with this example. Do you mean the unit cap = 2*50µm2 = 50 X 50 um2 ? or = 100um2 ?

In my calculation I thought of a unit cap = 2*50µm² = 100µm². That's why the calculated σ value is lower by a factor of √2 .

If it is 50 X 50um2, that is to say, one capacitor is 50X 50um2, and the other consists of 4 50 X 50um2 , then the result I got is 230/2 = 115 ppm. What's wrong?

You need to compare the mismatch of the single cap against each of the others, so the result stays at 230ppm, see my worst case consideration above. If you don't need to consider the worst case, you could statistically calculate with a σ value of 230ppm/√2 , but not half of the original value, because you probably won't position the 4 unit caps in the same direction away from the "1" unit cap, but symmetrically.

 

[urian]

No, I don't think so: You have to compare the mismatch of the unit cap "1" to both of the 2 other unit caps, which in both cases still is 0.023%. So for worst case (both of the "2" caps tend to mismatch into the same direction), the overall mismatch of the 1:2 (or 1:4 or 1:8) configuration still is 0.023%. Statistically it will be a bit less (because parameter mismatch tends to increase or decrease in one direction), for an industrial project, however, you always need to consider the worst case, unfortunately

So, if the unit cap is 50um X 50um, then the mismatch between capacitor pair is always 0.023% no matter what the capacitor ratio is, 1:2 or 1:3, or 1:5 or whatever?

In my calculation I thought of a unit cap = 2*50µm2 = 100µm2. That's why the calculated σ value is lower by a factor of √2 .

If the unit cap = 2*50µm\[{ 2}^{ }\] = 100µm\[{ 2}^{ }\]. And the unit cap the foundry given is 50X50=2500um\[{ 2}^{ }\], why there is only \[\sqrt{ 2}\] reduction?

You need to compare the mismatch of the single cap against each of the others, so the result stays at 230ppm, see my worst case consideration above. If you don't need to consider the worst case, you could statistically calculate with a σ value of 230ppm/√2 , but not half of the original value, because you probably won't position the 4 unit caps in the same direction away from the "1" unit cap, but symmetrically.

I wonder whether in the case of 1:4 ratio, there is sum square root relationship between each cap.

 

[erikl]

So, if the unit cap is 50um X 50um, then the mismatch between capacitor pair is always 0.023% no matter what the capacitor ratio is, 1:2 or 1:3, or 1:5 or whatever?

Yes, in a worst case consideration, because all of the multiple caps could deviate in the same direction, e.g all of them could have a deviation of 0.023%, hence the overall deviation for the 1:n configuration would stay at this value.

Statistically - for a symmetric configuration - this is not the case, of course - that's why symmetrical alignments are used for such 1:n configurations. The achievable deviation decrease, however, depends on the symmetry used and on the geometrical direction(s) of the parameter deviation change (and their (non-)linearity) on the chip/wafer (mainly dielectric thickness and/or ε variation, in case of capacitors). No simple way to account for.

If the unit cap = 2*50µm\[{ 2}^{ }\] = 100µm\[{ 2}^{ }\]. And the unit cap the foundry given is 50X50=2500um\[{ 2}^{ }\], why there is only \[\sqrt{ 2}\] reduction?

This is a misunderstanding: I thought of the comparison of two single 7µm x 7µm (≈50(µm)²) caps (so each one has ≈50(µm)²) in a 1:1 configuration, with 4 such caps, positioned in a symmetric quadruple, each two cross-wise linked, so ≈100(µm)² for each of these connected pairs, again in a 1:1 configuration.

I wonder whether in the case of 1:4 ratio, there is sum square root relationship between each cap.

If you'd know their respective (symmetry- and direction-caused) deviation, you could exactly calculate the overall deviation. For a 1:4 star configuration (the "1" cap in the center) for instance, for a 2-D linear variation change in arbitrary direction such symmetrical configuration would totally cancel the deviation - that's why symmetrical configurations are important. There's no simple way to account for the real residual deviation - if you can't get measured data for symmetrical configurations from the fab/foundry, I think. If so, they usually won't guarantee them ...

You could try (and error) this sum square root relationship by measuring the chips of a trial run - at least this seems better than relying on total deviation cancellation by symmetry or taking the real estate cost of a huge area overhead for the absolutely pessimistic worst case consideration of no deviation reduction at all.

My opinion - don't know if this is helpful. My (good) experience was: take that unit area which corresponds to (or is better than) the needed accuracy -- and see that you don't ruin that accuracy by routing parasitics!

 

[urian]

Hi,erikl

If you'd know their respective (symmetry- and direction-caused) deviation, you could exactly calculate the overall deviation. For a 1:4 star configuration (the "1" cap in the center) for instance, for a 2-D linear variation change in arbitrary direction such symmetrical configuration would totally cancel the deviation - that's why symmetrical configurations are important. There's no simple way to account for the real residual deviation - if you can't get measured data for symmetrical configurations from the fab/foundry, I think. If so, they usually won't guarantee them ...

You could try (and error) this sum square root relationship by measuring the chips of a trial run - at least this seems better than relying on total deviation cancellation by symmetry or taking the real estate cost of a huge area overhead for the absolutely pessimistic worst case consideration of no deviation reduction at all.

My opinion - don't know if this is helpful. My (good) experience was: take that unit area which corresponds to (or is better than) the needed accuracy -- and see that you don't ruin that accuracy by routing parasitics!

I think in your option, the statistically mismatch value is better than the worst case, right?
My fellow taught me the method he used for cap. mismach calculation, that is, if the unit is C (area ) and its Std.dev. is σ, then there are two capacitors composed of the unit cap. C with raito a:b, we can get the mismatch sqrt((1/a)+(1/b)) * σ. I wonder whether it is the statistically method you menioned above? And the result calculated by this method is less than yours. So it is not relate to the worst case? And the worst case is that the mismatch will not change with regard to ratio?

 

[erikl]

I think in your option, the statistically mismatch value is better than the worst case, right?

Less, yes - for symmetrical (common centroid) configurations.

My fellow taught me the method he used for cap. mismach calculation, that is, if the unit is C (area ) and its Std.dev. is σ, then there are two capacitors composed of the unit cap. C with raito a:b, we can get the mismatch sqrt((1/a)+(1/b)) * σ. I wonder whether it is the statistically method you menioned above?

No, I don't know this method for usage in capacitor ratio (with this above equation, the result would always be >1*σ :roll:, converging to 1*σ for large "b" values). But a well known statistical method for usage in systems with closely related parts is 1/sqrt(a^2+b^2) * σ, so this might be a good method for estimating the overall mismatch of an a:b ratio system - if one doesn't know a better one in lack of a:b mismatch data for symmetrical configurations from the fab.

And the result calculated by this method is less than yours.

But: see above :!:

So it is not relate to the worst case?

No. The worst case is if all "b" caps have the worst case mismatch in the same direction, then the original σ value will not be improved - a rather unlikely case. Worst cases always are unlikely - but they can occur, and they should be accounted for, if economically reasonable. You also account for other combined (and so rather unlikely, too) PVT worst cases, don't you?

For a high volume product, the problem always is to find a good balance between chip cost (capacitor area, in your case) and yield. The updated square root σ method (s. above) might set a good compromise, if the cap area really is a relevant part of the whole chip.

And the worst case is that the mismatch will not change with regard to ratio?

Yes, s. above.

 

[urian]

Hi,erikl

I see that you have emphasized on symmetrical (common centroid) configuration many times. But in the foudry DR files, they didn't mention the symmetrical configuration with two ratio caps. Take the 0.023% Std. dev. for example, it gives the caps layout architecture like below:
.
. ...................................................X X
. ..............................................X
. ...................................................X X

where X is unit cap. Then it gives the 1:4 ratio Std.dev at the beginning of this post. But I think this configuration is not a symmetrical one, then what is the usage of the Std.dev. value given by them while we always layout as symmetrical?


The method my friend used can be seen in the pic below:



Is this calculation right?

 

[erikl]

I see that you have emphasized on symmetrical (common centroid) configuration many times. But in the foudry DR files, they didn't mention the symmetrical configuration with two ratio caps. Take the 0.023% Std. dev. for example, it gives the caps layout architecture like below:
.
. ...................................................X X
. ..............................................X
. ...................................................X X

where X is unit cap. Then it gives the 1:4 ratio Std.dev at the beginning of this post. But I think this configuration is not a symmetrical one, then what is the usage of the Std.dev. value given by them while we always layout as symmetrical?

Don't know. I think you have to ask your foundry. Usually the given mismatch σ value is for asymmetric (but adjacent) device configurations - an important figure e.g. for the offset estimation of a differential amplifier (input) stage.

The method my friend used is below:

I'm sorry: this math presentation is practically illegible. The forum's LaTeX service unfortunately isn't standard, so there's no simple formatting here (if I ever use it, I use the Preview function until it works correctly). It's mostly more convenient to use the standard symbols like "/" for division, "^2" for square and the "√" for square root. You find it - together with more math symbols and greek characters - where you found the "σ" symbol.

You can embed the whole equation system into

 tags to allow for individual formatting.

[COLOR="silver"]- - - Updated - - -[/COLOR]

[QUOTE="urian, post: 1209614, member: 248767"] The method my friend used can be seen in the pic below:

[ATTACH=CONFIG]87960[/ATTACH]

Is this calculation right?[/QUOTE]
 
Now it's legible ;-), thank you. But the result \[sqrt{{\frac {1} {a}}+{\frac {1} {b}}} \] - for a=1 and b>1 - is always >1 , as I already told you [URL="https://www.edaboard.com/threads/282135/#post1209170"]in my post above[/URL]. Didn't you read it, or are you happy with it?

PS: I didn't take the trouble to retrace your friend's math, because it apparently leads to a wrong result.

 

[urian]

Usually the given mismatch σ value is for asymmetric (but adjacent) device configurations - an important figure e.g. for the offset estimation of a differential amplifier (input) stage.

So if we use symmetrical configuration, the calculation result using this δ is worse than practice?

I'm sorry: this math presentation is practically illegible. The forum's LaTeX service unfortunately isn't standard, so there's no simple formatting here (if I ever use it, I use the Preview function until it works correctly).

Well, I am not aware of it before, so I have to type them in Mathtype and save as pic. :-(

Now it's legible , thank you. But the result - for a=1 and b>1 - is always >1 , as I already told you in my post above. Didn't you read it, or are you happy with it?

PS: I didn't take the trouble to retrace your friend's math, because it apparently leads to a wrong result.

Yes, the result is always >1 by this method so I can never love it.:smile: I think there may be something wrong when either of them equal 1 as the result will be always>1. But when a>1 and b>1, the result is ≦1 and it sounds reasonable. But most of all, he is confident about his method and I have no idea how to defeat him cause I am confused at all..:-(

 

[erikl]

So if we use symmetrical configuration, the calculation result using this δ is worse than practice?

Seems so, yes.

Yes, the result is always >1 by this method so I can never love it.:smile: I think there may be something wrong when either of them equal 1 as the result will be always>1. But when a>1 and b>1, the result is ≦1 and it sounds reasonable.

That's true. But if you use a:b=2:2 or a:b=4:4 instead of a:b=1:1 , you each time get different results. Same for 2:4 or 3:6 or 4:8 instead of 1:2 . Now tell me: is this an acceptable method?

But most of all, he is confident about his method and I have no idea how to defeat him cause I am confused at all..:-(

Ok. Thinking twice, I hope I now know why your friend's algorithm isn't applicable to your σ calculation problem: in the beginning of the equation system in your above image it states the validity for uncorrelated mismatches, whereas I think in highly symmetric configurations the mismatches are also highly correlated.

That's why I gave you the context 1/sqrt(a^2+b^2), which is valid for highly correlated systems. For medium correlated systems, the context 1/sqrt(a+b) is often used, which results in lower attenuation for rising b values.

Now don't ask me where from I got these contexts: I still have them in my mind because I've used them (for different, but similar symmetric problems) ages before, so you'd have to grab them yourself from appropriate literature.

 

[urian]

That's true. But if you use a:b=2:2 or a:b=4:4 instead of a:b=1:1 , you each time get different results. Same for 2:4 or 3:6 or 4:8 instead of 1:2 . Now tell me: is this an acceptable method?

Is it caused by the uncorrelated assumption between caps. mismatch as you have explained below? So 2:4 or 3:6 or 4:8 will get different result because the number of unit cap is different.

Ok. Thinking twice, I hope I now know why your friend's algorithm isn't applicable to your σ calculation problem: in the beginning of the equation system in your above image it states the validity for uncorrelated mismatches, whereas I think in highly symmetric configurations the mismatches are also highly correlated.

That's why I gave you the context 1/sqrt(a^2+b^2), which is valid for highly correlated systems. For medium correlated systems, the context 1/sqrt(a+b) is often used, which results in lower attenuation for rising b values.

In a word, my friend's method is not optimized as he didnt take correlation into account which exists in practical layout. If we calculate caps area in this way, we will get a larger size than it should be, right? Furthemore, how can we decide the degree of correlation of a configuration, for common centroid layout, it is a highly or medium correlated system?

Now don't ask me where from I got these contexts: I still have them in my mind because I've used them (for different, but similar symmetric problems) ages before, so you'd have to grab them yourself from appropriate literature.

I will use your equations directly in my project for it has been proven by your career. And I will pick it up from some literatures.

 

[erikl]

Is it caused by the uncorrelated assumption between caps. mismatch as you have explained below? So 2:4 or 3:6 or 4:8 will get different result because the number of unit cap is different.

Yes, I'd think so.

In a word, my friend's method is not optimized as he didnt take correlation into account which exists in practical layout. If we calculate caps area in this way, we will get a larger size than it should be, right?

Yes, at least for a 1:n configuration.

... how can we decide the degree of correlation of a configuration, for common centroid layout, it is a highly or medium correlated system?

I think this depends on the

1. process control by the foundry
2. degree of (common centroid) layout symmetry achieved

If you can't get symmetry-dependent mismatch data from the foundry, the only way is to estimate the degree of correlation: Personally, I'd consider a perfect *) layout symmetry (achievable e.g. for 2:2 and higher m:n configurations, if necessary with additional dummies) as highly (or strongly) correlated, and a less perfect configuration (e.g. 1:1 , 1:2) as correlated to medium degree.

*) perfect would also include corresponding perfectness of routing/parasitics symmetry

 

[urian]

Hi,erikl,
thank u so much, you really has helped me a lot in understanding cap mismatch with related to correlation. I am very appreciate it.
Furthemore,your reply looks beautiful;-)

Regards
urian

 

[erikl]

Furthemore,your reply looks beautiful;-)

Thank you, Urian!

Yes, this was an interesting discussion. One more note:

Above mentioned perfectness needs to be defined in numbers: The (non-)accuracy of the symmetry (including parasitics) should be a bit better than the required resolution, for your 8bit ADC this would mean ≦ 1/2 * LSB or layout asymmetry ≦ 1/512 ≈ 0.2% .

Good luck! erikl

 

[urian]

Got it:grin: