how to calculate area cost in verilog design using XILINX?

[neefa]

area cost in xilinx

hi frz,
could any one plz tell me hw to calculate area cost in verilog design using XILINX.
thx.

 

[nxtech]

Re: area cost in xilinx

What do you mean by area cost? Part price, routing resources used, what?

Please elaborate so we can help you.

E

 

[tomasulo]

Re: area cost in xilinx

Hi,

Do you mean FPGA Resorces?

You can can it after P&R report.
Also, you can have a prevision after Sythesis report
For a place implementation inside the FPGA, use The Floorplanner editor.
All from Xilinx ISE tool.

Tomasulo

 

[neefa]

Re: area cost in xilinx

hi,
i need to calculate the area consumed and power consumption.but these are not directly given in the synthesis report or PR report.


whether routing resources mean the no of slices,FF etc what we get in the synthesis report?

tomasulo,plz eloborate floorplanner editor.

thx.

Added after 5 hours 46 minutes:

hi,
what is the correct procedure for calculating delay.
In the syhthesis report we r getting maximum combinational path delay,whether we can take this value?
thx

 

[nxtech]

Re: area cost in xilinx

If you are interested in area consumed that information is indeed given to you. It is listed as a percentage of the total device resources. This is then broken down to tell how many flip flops, how many registers, etc. have been utilized.

As for the power consumption you will have to use yet another tool, the power calculator, and refer back to your P&R report to get the information you need to input into the power calculator.

E