Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to calculate ADC Sampling Rate

Status
Not open for further replies.

soumen21

Member level 4
Joined
May 7, 2011
Messages
69
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Activity points
1,751
According to datasheet, the ADC clock frequency should be
between 50kHz and 200kHz to ensure 10-bit effective resolution. 50kHz ADC clock frequency is chosen. Then the sampling frequency becomes ~3800 SPS.
Vref = 5V, Vin =2.5V

How the sampling frequency is calculated ?
 

alexan_e

Administrator
Joined
Mar 16, 2008
Messages
11,895
Helped
2,021
Reputation
4,158
Reaction score
2,031
Trophy points
1,393
Location
Greece
Activity points
64,377
I assume that you are asking for AVR.
The datasheet explains it in the ADC section, In ADCSRA register the bits 2-0 control the division factor

Code:
•  Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits 

 These bits determine the division factor between the XTAL frequency and the input 
 clock to the ADC. 

 Table 76.    ADC Prescaler Selections 

        ADPS2                ADPS1                ADPS0                    Division Factor 

           0                    0                    0                             2 

           0                    0                    1                             2 

           0                    1                    0                             4 

           0                    1                    1                             8 

           1                    0                    0                            16 

           1                    0                    1                            32 

           1                    1                    0                            64 

           1                    1                    1                            128

Alex
 

soumen21

Member level 4
Joined
May 7, 2011
Messages
69
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Activity points
1,751
Hi Alex,
Thanks for your reply. Yes, it is for AVR. But I could calculate the approximate value as mentioned (~3800 SPS) in the application note using the divisor table. Can you please show me the calculation ?
 

alexan_e

Administrator
Joined
Mar 16, 2008
Messages
11,895
Helped
2,021
Reputation
4,158
Reaction score
2,031
Trophy points
1,393
Location
Greece
Activity points
64,377
you divide the clock with the division factor, for example 8000000/128=62500Hz
This frequency should be between 50000Hz and 200000Hz.
The normal conversion takes 13 cycles so the sample/sec is ADC frequency/13

Alex
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top