how to calculat Peak Leakage Power for CMOS inverter ?

[Yassir_eldo]

Good morning,

Please how can I calculate the "Peak leakage power" of a CMOS inverter ? I have alrady calculate the "Rise delay" the "Full Delay", I have also the "Vdd" , "Imax" and "f=frequency".

Thank you in advance;

 

[erikl]

"Peak leakage power" = max_supply_voltage x max_leakage_current , where max_leakage_current is the worst case leakage current @ fastest_process, max_supply_voltage and highest_temperature conditions. You'd also have to consider your input condition, whereby the worst case condition is the max. voltage distance from either GND or VDD. That max_leakage_current will involve leakage current + cross current through both MOSFETs.

 

[Yassir_eldo]

thank you for your answer, but I did not understand the second part: concerning " voltage distance from either GND or VDD. That max_leakage_current will involve leakage current + cross current through both MOSFETs".

What I want realy to understand is how they have calculate the Peak Leakage Power in P.P: 3 of the document enclosedView attachment Invertor-SOIvsBulkisdm097.pdf

Thank you in advance

 

[erikl]

I did not understand the second part: concerning " voltage distance from either GND or VDD. That max_leakage_current will involve leakage current + cross current through both MOSFETs".

This would only be relevant if the input voltage were less than the full supply voltage, which apparently is not the case in the paper you mention - so forget about it.

What I want realy to understand is how they have calculate the Peak Leakage Power in P.P: 3 of the document enclosedView attachment 88682

I think it is the folding (multiplication) of a single Output Voltage times Output Current switching spike (means: multiplication of the areas of corresponding spikes, divided by the time of their duration), what isn't traceable from the curves presented on page 2. Just the reason for the difference is explained below Table 1 .