How to build a simple clock detector?

[gianbo85]

Hi Everybody,

for a university project I have the need to check for the presence of a trigger-in signal in my apparatus.

- The signal is a digital clock with a variable frequency in the range 1MHz - 50MHz.

- I can detect this signal either from the negative output of a LVPECL XOR (Low level at 1.6V, High Level at 2.4V) or from the output of an opamp (Low level at 0V, High level at 200mV)

- I just need to generate a high/low level to send to a PIC microcontroller in case the trigger in signal disappears.

Any Idea? I thought about a superdiode (opamp+diode) plus a tuned RC circuit and a comparator in the end (see picture).

SInce space on my pcb is a problem I would like to find a simpler circuit without the use of two opamps!

Thanks

Gianluca

 

[dick_freebird]

I'd suggest a simpler digital transition detector (like an XOR,
with clk to one and delayed clk to the other input) to drive a
"reset switch", and your RC network tuned to maybe
2-5uS time constant, and a Schmitt buffer after it.

 

[karesz]

Also, if Im right:
you need a change in logic level to send to your PIC if i.e. the LVPECL output is no more high=2.4V, also went/changed to "0=1.6V?
Wher is comparing reference voltage level pls of you PIC, or is it a TTL compatible Input?
How much Volts is it?
Usual s if a ECL IC supplyd with +3V3 or 5V than=PECL!
A comparing logic level(Vbb) is at max ca. +1.9V (Vcc-Vbb, 3V3-1V35), if you hase PECL in system; is it supplyed (as lvpecl per definition is) with +3v3 or not?
Also, what you need is no more as a comparator at +Vbb referenced, in concret case between 1355 & 2075mV, practically to middle, as the attachement tells you too.
Compare pls for +1.75V and is your circuit in extrems functioning too, but you need a good Uref!
Other possibilty is onlya SO8 IC (NB100ELT23L)
as Level Converter to apply and works up to 160MHz, see attachement...
K.

 

[gianbo85]

Thanks for the reply!

Dick's idea is good but the component count is pretty much the same as mine plus to delay the clock I need a long trace on my pcb or a delayer and that means a lot of space required.

Karesz, if you read my description more carefully, I won't feed the LVPECL signal directly to the PIC, that won't work as you suggested.

My collegue suggested an alternative using a BJT: connecting the base of a PNP BJT to the LVPECL signal, its source to a Vdd voltage through a resistor and its drain to a capacitor.

In this way the BJT behave like a square-wave current generator. Dimensioning the R and the C I can create a voltage ramp on the capacitor and using the ADC or the comparator on the pic I can check if a certain threshold it crossed.

Once the Vt is crossed I can discharge the C through another pin of the PIC and a diode.

I tried to simulate the circuit with Vdd= 3V, R = 1k and clock signal between 1.6V and 2.4V. If I put a resistor on the drain everything works fine but with a capacitor I can't get a voltage ramp!

Any idea?

Have a nice day

 

[karesz]

@gianbo85
BJT has E,B & C, but I would have a basis resistor too and so on... Really you must a switched Current generator build.
K.

 

[gianbo85]

@ Karesz. How could I have said that a BJT has a drain and a source? :-s ehehe... Thanks for the correction.

I like the idea of the current generator but I can't get it to work, at least on my SPICE simulator. I am quite sure I don't need a base resistor since the current is fixed through the emitter resistor and the base voltage.

The problem is when I swap the resistor on the collector with a capacitor. Instead of getting a voltage ramp I get a more or less constant voltage. What's wrong with my configuration?

Obviously, if anyone can suggest an easiest way to implement my clock detector... ideas are welcomed!

Gianluca

 

[karesz]

hi Gianluca,
You can load/switch from PECL output over a serial Schottky (Cathode on ECL out) a serial resistor-capacitor between Vcc & GND_ C is to GND & i.e. 1..2K to Vcc...Common point of Cathode/R & C is output too.
Discharging must be possible with a switched parallel resistor on the C.
K.

 

[dick_freebird]

Well, here's one I sketched up over the course of a couple
minutes that seems to work. Very low actives count, but the
passives would be a bit chubby if integrated (more so, the
lower you want the minimum detect freq to be).