This question has been lingering in my mind for quite sometime.
I know how to do it in Verilog, e.g. below.
Code:
if (te0630_top_inst.cpu_top_inst.i_core_top.i_pipeline_top.i_alu_top.of_ex_operation_opcode.mnemonic ==
ALU_CMD_STOP) begin
$display (...something...);
end
I am also aware that in old style VHDL port mapping has to be done to bring out a signal which will not look as elegant as when the same is coded in Verilog.
So is it done in a similar fashion in VHDL-2008 (have no experience in this)?