How to avoid obtaining inconsitence biasing Values,while designing LowNoiseAmplifier

[hari_preetha]

I have designed the low noise amplifier(LNA) using pHEMT transistor. I have perfectly designed LNA at 2.3 GHz using coupling capacitors to bypass any AC components, I am sure that my designed LNA is correct.
But I have doubt on the stability setting

When I designed LNA at 2.3 GHZ, When I checked the stability, it shows the following values when linear (S-parameter) transistor is connected.

Stability started from 1.7 GHz and stability ended at 2.4 GHz

When nonlinear transistor is connected, LNA shows the following stability

Stability stated from 1.6 GHz and ended stability at 2.3 GHZ.

I have set the biasing points as Vgs = 565 mV and Vds = 3 V, Ids = 60 mA.

But When I connected LNA PCB mounted components, it is showing Vgs= - 1.02 V, Vds = 4.3 volts, Ids = 300 mA.

I have set the different biasing points and am getting negative Vgs, more Vds and more Ids.

There is no doubt in my LNA design. I have doubt in the stability range setting. For simulation, above mentioned stability values I have set it for the linear and non linear simulation.

For getting proper stability at 2.3 GHz, lower value what value it must be started and it must be ended till upto what frequency to avoid the inconsistent values of the biasing. Can you clarify it.

What could be the other reasons for getting the inconsistent biasing values, while designing LNA.
You are all experienced people, share your experience, I will be benefited and others also benefited.

 

[BigBoss]

Stability is not considered in the band which is interested only, instead stability should be checked until fmax.Therefore, your LNA may work in the band but it may also oscillate somewhere at out of band.
What type of pHEMT do you use ?? D-Type or E-Type ??
You LNA is probably oscillating somewhere but your don't know.I understand this from absolutely different OP compare to simulation.

 

[D.A.(Tony)Stewart]

Stabilty analysis requires an image of layout, schematic and test results. Click add image then select sources, upload , then copy jpg links and add image by url's or other method using add image icon from local jpgs

 

[hari_preetha]

Stability is not considered in the band which is interested only, instead stability should be checked until fmax.Therefore, your LNA may work in the band but it may also oscillate somewhere at out of band.
What type of pHEMT do you use ?? D-Type or E-Type ??
You LNA is probably oscillating somewhere but your don't know.I understand this from absolutely different OP compare to simulation.

I am using E-PHEMT, avago ATF54143. I am exactly working at 2.3 GHz. As I asked in the posting # 1, what must be minimum value to set stability to start and what must be end value of stability to obtain consistent Biasing values. I am working in the narrow band. Can you clarify.

 

[volker@muehlhaus]

Ids = 300 mA.

I am using E-PHEMT, avago ATF54143.

Your transistor is dead now. Absolute maximum rating is 120mA Ids.

 

[hari_preetha]

Your transistor is dead now. Absolute maximum rating is 120mA Ids.

Yes, absolutely transistor is spoiled. What could be reasons showing inconsistent biasing values.Event though in simulation, it is showing correct values. Is it any faulty range of stability values, what I set for 2.3 GHz design of LNA.

 

[afz23]

PHemts are highly ESD sensitive,did you take precautions while handling,soldering and testing this device?
Did you take precautions in connecting gate first and drain supplies later?

 

[hari_preetha]

PHemts are highly ESD sensitive,did you take precautions while handling,soldering and testing this device?
Did you take precautions in connecting gate first and drain supplies later?

I got soldered from one of the export, he knows very well about the micro soldering. But he doesn't know first gate should solder, later drain ...etc. I should have told it. I didn't tell it. Because, I don't know, what are the precaution we have to take while soldering microwave passive and active components.
Please tell me, what are the precautionary measurements we have to take, while placing R,L, C and Transistor to the board.
While carrying out next work, we can take all the precautionary measurements
How to avoid the inconsistent results.

 

[volker@muehlhaus]

How to avoid the inconsistent results.

As BigBoss has mentioned in post #2, your LNA must be stable at all frequencies. If your design is only stable in a limited frequency band, it is a bad design and will cause trouble. You need to redesign the LNA to be stable.

As BigBoss has mentioned in post #2, the strange bias measurement seems to be a result of LNA oscillation. Otherwise, you should have Ids=0 at Vgs= - 1V.

 

[BigBoss]

Another issue may be applying voltages...
I presume that Vdd and Vgs sources are separate...
If you apply Vdd before Vgs, while Vdd has its own voltage Vgs will be 0 and it's out of operating voltage for Vgs and FET might be burned during connection of Vdd...

 

[hari_preetha]

Another issue may be applying voltages...
I presume that Vdd and Vgs sources are separate...
If you apply Vdd before Vgs, while Vdd has its own voltage Vgs will be 0 and it's out of operating voltage for Vgs and FET might be burned during connection of Vdd...

Thank for your advices. What I did is, totally 3 transistors connections are in my circuit, unknowingly one of the transistor drain and source was not connected, remaining gate and source was connected. When I connected the power supply and switched on, it was showing Vgs = -1 V, Vds = 4 V, and Ids = 170 mA. After noticing inconsistent results, I rechecked the circuit, there was no connection of drain and source to one of transistor.
After we removed all three transistors and replaced with new three transistors, again it was showing inconsistent results. I thought that once it starts showing inconsistent results, it will never show the consistent results. Can you clarify it. We can take all these mistakes as precautionary in the next design.

 

[BigBoss]

Thank for your advices. What I did is, totally 3 transistors connections are in my circuit, unknowingly one of the transistor drain and source was not connected, remaining gate and source was connected. When I connected the power supply and switched on, it was showing Vgs = -1 V, Vds = 4 V, and Ids = 170 mA. After noticing inconsistent results, I rechecked the circuit, there was no connection of drain and source to one of transistor.
After we removed all three transistors and replaced with new three transistors, again it was showing inconsistent results. I thought that once it starts showing inconsistent results, it will never show the consistent results. Can you clarify it. We can take all these mistakes as precautionary in the next design.

As I said before, connect Vgs before Vdd.You have namely to connect Vgs to max. negative voltage-let say -5V- at the beginning before connecting Vdd then you should connect Vdd and increase Vgs until you obtain the right currrent.
General procedure looks like that and do not connect any measurement equipment especially to Gate unless you see the good currrent consumption on the current panel of power supply.Otherwise the LNA can start to oscillate and this may damage the transistors.

 

[hari_preetha]

As I said before, connect Vgs before Vdd.You have namely to connect Vgs to max. negative voltage-let say -5V- at the beginning before connecting Vdd then you should connect Vdd and increase Vgs until you obtain the right currrent.
General procedure looks like that and do not connect any measurement equipment especially to Gate unless you see the good currrent consumption on the current panel of power supply.Otherwise the LNA can start to oscillate and this may damage the transistors.

Sorry for prolonged discussion. As you suggested, I didn't connect independently gate and drain biasing voltages. I have connected directly 3 V from power supply to the Drain using inductance and using voltage divider resistors and inductance making 565 mV to the Gate. Once power switch on, gate and drain voltage appear automatically, I can't give independently gate voltage, later drain voltage.

If I switch on once the power supply, definitely drain voltage also appear along with gate voltage.

Even if we replace all three transistors with new transistors and perfect connections also. Once it starts to show inconsistent results, it will never show consistent results. Is it correct ?

 

[volker@muehlhaus]

one of the transistor drain and source was not connected (...) Vgs = -1 V, Vds = 4 V, and Ids = 170 mA.

How can you have 170mA drain current if the drain is not connected? Something is wrong with your measurements of the bias condition.