rocking_vlsi
Member level 5
Hi
Some part of my verilog code is like this.
As of my knowledge for loop will be unrolled while synthesis. Since memory read cannot be parallel in my case... How to avoid for loop unrolling during synthesis.
Some part of my verilog code is like this.
Code:
for(i=0;i<10;i++) begin
for(j=0;j<10;j++)begin
acc<=acc+read_memory();
end
end
As of my knowledge for loop will be unrolled while synthesis. Since memory read cannot be parallel in my case... How to avoid for loop unrolling during synthesis.