Re: Can glitches be avoided?
FPGA use LUT for evaluating expressions. The table is simply a truth table. It basically evaluate expression using a ROM structure. The input is taken as an address, and the data at that address in the Look-Up Table (LUT) is output as the result.
Suppose you have 4 inputs, and that you have '0101' at input, and at that address, you have a 1, that you'll see a '1' at output. Suppose you now wish to input '1001'. The problem is that if you change the input value, due to routing delays, it is possible that for a fraction of a second (a few nanoseconds), when passing from '0101' to '1001', you may get a bit ariving faster than the other. So, you may get an intermediate input like '0001' or '1101'. Suppose that the content at address '1001' in the LUT is also 1, but at both addresses '1101' and '0001', you have a zero, then you may get a glitch.
So, for example, it is not good to use combinational logic or LUT as an input of a register CLK input.