How to assign a value async using systemverilog?

[lty]

I want to test a fifo. the fifo read interface have three signals "rd, rdata, nempty".

I hope when nempty is valid, the testbench will assert rd to begin a read operaion.

But in SV program structure, the rd sigal always delay one cycle, maybe because clocking structure.

Can anyone give me one example how to implement this idea using SV.

In verilog, I think I can use "assign rd = nempty".

In SystemVerilog, How?

Thank you!

---------- Post added at 17:13 ---------- Previous post was at 17:01 ----------

I find the following code can implement my idea. Is it a good way?

initial begin
fork
forever begin
@( fifo_rd_if.nempty )
fifo_rd_if.rd = fifo_rd_if.nempty;
end
join_none
#100;
$exit;
end