wjxcom said:Hi, all: the file in the attachment is a OPA and this circuit puzzles me.
1.why we must use the Q6 and Q7 which act as a class B push-pull output stage? and why Q6 and Q7 can act as a class B push-pull output stage?
2.the dc biasing is designed so that Q8 and Q9 have equal-value small gate-to-source dc bias. This maximizes the linear Vout range. I do not know why.
wjxcom said:Hi, all: the file in the attachment is a OPA and this circuit puzzles me.
1.why we must use the Q6 and Q7 which act as a class B push-pull output stage? and why Q6 and Q7 can act as a class B push-pull output stage?
2.the dc biasing is designed so that Q8 and Q9 have equal-value small gate-to-source dc bias. This maximizes the linear Vout range. I do not know why.
but q6 and q7 make a level shifter which let the first stage can push-pull output stage q8-q9, but i think this op ll need miller compensation.
do you know whitch pin of Q7 is SOURCE?Q6 and Q7 are used as source follower.this provides adjustable gate voltage for Q9 to have maximum o/p range.otherwise if Q6 and Q7 were not used,Q9 will start to flow constant current becuase having constant gate voltage.this will give fixed maximum voltage(upper limit).
Davood Amerion said:avinash
do you know whitch pin of Q7 is SOURCE?
how you say Q7 is source follower?
In source follower GATE is input and SOURCE is output
wjxcom said:Hi, all: the file in the attachment is a OPA and this circuit puzzles me.
1.why we must use the Q6 and Q7 which act as a class B push-pull output stage? and why Q6 and Q7 can act as a class B push-pull output stage?
2.the dc biasing is designed so that Q8 and Q9 have equal-value small gate-to-source dc bias. This maximizes the linear Vout range. I do not know why.
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