Greetings ... can someone explain to me how I can load the ip core of a FIFO 9.3 with the tcl console of ISE 14.5? I have been trying to edit a l1_top.prj file where all the source code and ip cores are loaded for my project. But I am having trouble adding the ip core of a FIFO in the following way.
Code:
vhdl work ../../../build/coregen/l1_coregen_tx_data_fifo/l1_coregen_tx_data_fifo.vhd
vhdl work ../../../build/coregen/l1_coregen_wbus_client_fifo/l1_coregen_wbus_client_fifo.vhd
The errors I am getting are shown in the attached image.
One way to check what you need in the prj file is to make a new project and only add the xci file to the project (and maybe a wrapper file) and generate the core. Save off the project and see what was added.
If I remember correctly I normally added xci files not the HDL files to the project file in ISE. This is the problem I have with using the GUI loading cores usually requires loading a bunch of "hidden" files from somewhere else that the tools take care of automatically. Makes it hard to script builds because of it.