How to add the ip core of a FIFO using tcl console in ISE 14.5?

[Cesar0182]

Greetings ... can someone explain to me how I can load the ip core of a FIFO 9.3 with the tcl console of ISE 14.5? I have been trying to edit a l1_top.prj file where all the source code and ip cores are loaded for my project. But I am having trouble adding the ip core of a FIFO in the following way.

vhdl work ../../../build/coregen/l1_coregen_tx_data_fifo/l1_coregen_tx_data_fifo.vhd
vhdl work ../../../build/coregen/l1_coregen_wbus_client_fifo/l1_coregen_wbus_client_fifo.vhd

The errors I am getting are shown in the attached image.

Any help is welcome.

 

[ads-ee]

If I recall correctly (haven't used ISE for 8+ years) I think you're missing a lot of the lower level files that are generated by coregen for FIFOs.

 

[Cesar0182]

if you are right, the code I am using to load the ip cores are the same ones used by the ISE GUI. I thought this would work.

 

[ads-ee]

One way to check what you need in the prj file is to make a new project and only add the xci file to the project (and maybe a wrapper file) and generate the core. Save off the project and see what was added.

If I remember correctly I normally added xci files not the HDL files to the project file in ISE. This is the problem I have with using the GUI loading cores usually requires loading a bunch of "hidden" files from somewhere else that the tools take care of automatically. Makes it hard to script builds because of it.

 

[Cesar0182]

I did what you recommended, but I still see the GUI still using only the same command.

When creating an ip core in Vivado, it is true that the .xci file is generated and loaded with the following command.

read_ip ../../../build/coregen/l1_coregen_tx_data_fifo/l1_coregen_wbus_client_fifo.xci

but the ip core generator in ISE creates .xco files and something like:

read_ip work ../../../build/coregen/l1_coregen_tx_data_fifo/l1_coregen_wbus_client_fifo.xco

neither "coregen work" or "ip work".

 

[dpaul]

The following might be of help-

Working with CORE Generator IP