how to add delay with out using "after some time" command.

[surerdra]

i written a program, latch is used as a component , when i simulate it no errors, but when i give test bench, output not came it is undefind up to some
time, and test bench also not shown after what happen while i use < run XX seconds>.


when i use "after 10ns" like delay in latch internal signals , the output came . i need output with out giving that delay , what i do?

 

[K-J]

i need output with out giving that delay , what i do?

Post your code so somebody can try to figure it out.

Kevin Jennings

 

[lichenjiee]

You must give an initial signal, simulation before you

 

[surerdra]

my code need 4 input clock signals(plus - 10 us clock, minus - 90 degree phase shift with plus,
clock0 - 500 ns clock, clock1 - 180 phase shift with clock0 )


here i declared some components declared in package, then called in main program .

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
   port(nin: in std_logic;
          nout: out std_logic);
end not1;         
architecture behavioral of not1 is
begin
 
 nout <= not nin;
 end behavioral; 
 --------------------------------------------------------
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity nand1 is
 port(a,b : in std_logic;
      c : out std_logic);
end nand1;
architecture behavioral of nand1 is
begin
c <= a nand b;
end behavioral;
--------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff1 is
 port(d,clk,clrn: in std_logic;
                   q: out std_logic
      );
end dff1    ;
architecture behavioral of dff1 is
begin 
process(clk)
begin   
if clk'event and clk='1' then  
      if clrn='0' then   
         q <= '0';
      else
         q <= d;
      end if;
   end if;
end process;    
end behavioral; 
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff2 is
 port(d,clk: in std_logic;
                   q: out std_logic
      );
end dff2    ;
architecture behavioral of dff2 is
begin 
process(clk)
begin   
if clk'event and clk='1' then  
     
         q <= d;
      
   end if;
end process;    
end behavioral; 
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nor1 is
 port(m,n : in std_logic;
      o : out std_logic);
end nor1;
architecture behavioral of nor1 is
begin
o <= m nor n;
end behavioral;
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
package my_components is
--
component nand1 is
port(a,b : in std_logic;
         c : out std_logic);
end component;
--
component nor1 is
 
port(m,n: in std_logic;
              o : out std_logic);
end component;
--
component dff1 is
 
port(d,clk,clrn: in std_logic;
                   q: out std_logic);
end component;
--
component dff2 is
 
port(d,clk: in std_logic;
                   q: out std_logic);
end component;
 
--
component not1 is
port(nin: in std_logic;
          nout: out std_logic);
end component;  
--
end my_components;      
----------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.my_components.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity phase_detect is
port(plus,minus,clock :in std_logic;
     p0,m0 : out std_logic);
      
end phase_detect;
 
architecture Behavioral of phase_detect is
 
signal x,y,a0,a1,a2,a3,a4,a5,a6,a7: std_logic;
signal q1,q2,q3,q4,q5,q6,z,w : std_logic;
 
begin
 
u1: not1 port map(plus,x);
u2: not1 port map(minus,y);
u3: nand1 port map(plus,y,a2);
u4: nand1 port map(x,minus,a1);
u5: nand1 port map(plus,minus,a3);
u6: nand1 port map(x,y,a0);
u7: nand1 port map(a2,a5,a4);
u8: nand1 port map(a4,a1,a5);
u9: nand1 port map(a3,a7,a6);
u10: nand1 port map(a6,a0,a7);
u11:dff1 port map(a4,a6,q5,q1);
u12:dff1 port map(a5,a7,q5,q2);
u13:dff1 port map(a4,a7,q6,q3);
u14:dff1 port map(a5,a6,q6,q4);
u15:nor1 port map (q1,q2,z);
u16:nor1 port map (q3,q4,w);
u17:dff2 port map (z,clock,q5);
u18:dff2 port map (w,clock,q6);
u19:not1 port map (q5,p0);
u20:not1 port map (q6,m0);
 
 
 
end Behavioral;
----------------------------------------------------------------------------------
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nor11 is
 port(m,n : in std_logic;
      o : out std_logic);
end nor11;
architecture behavioral of nor11 is
begin
o <= m nor n;
end behavioral;
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sel is
port (s,r :in std_logic;
      qbar : out std_logic);
end sel;
 
architecture Behavioral of sel is
signal q0,q1 : std_logic:= '0';
begin
 
q0 <= s nor q1 after 100 ns   ;-- if  delay not given like this out put not came
q1 <= r nor q0 after 100 ns  ;
qbar <= q1;
 
end Behavioral;
--------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not11 is
 port(clk : in std_logic;
      clk1 : out std_logic);
end not11;
architecture behavioral of not11 is
begin
clk1 <=  not clk;
end behavioral;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and11 is
 port(m1,n1 : in std_logic;
      o1 : out std_logic);
end and11;
architecture behavioral of and11 is
begin
o1 <= m1 and n1;
end behavioral;
--------------------------------------------------------------------------------
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
package my_package is 
 
--
component phase_detect is
port(plus,minus,clock :in std_logic;
     p0,m0 : out std_logic);
      
end component;
--
component nor11 is 
port(m,n : in std_logic;
      o : out std_logic);
end component;
--
component sel is
port (s,r :in std_logic;
      qbar : out std_logic);
end component;
--
component and11 is
        
    port(m1,n1 : in std_logic;
      o1 : out std_logic);  
end component;
--
component not11 is
port(clk : in std_logic;
      clk1 : out std_logic);
end component ;
--      
end my_package;     
 
 
 
 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity phase_detectstage is
 
port (plus,minus,clock0,clock1 : in std_logic;
     count_in1,count_in2: out std_logic:='0';
      ref_meander : out std_logic:='0'
      );
      --pll_pls,pll_mns : out std_logic);
 
end phase_detectstage;
 
architecture Behavioral of phase_detectstage is
 
signal x1,y1,z1,w1 : std_logic:='0';
signal clock_f0,pll_pls,pll_mns : std_logic:='0';
 
begin
 
u7 : sel port map (x1,w1,z1);
u6: not11 port map (clock0,clock_f0);
u1: phase_detect port map (plus,minus,clock_f0,pll_pls,pll_mns);
u2 : and11 port map (pll_pls,clock1,x1);
 
 
u5 : and11 port map (clock1,pll_mns,w1);
--u3 : nor11 port map (x1,z1,y1);
--y1 <= x1 nor z1;
--u4 : nor11 port map (y1,w1,z1 );
--z1 <= y1 nor w1;
 
count_in1 <= x1;
ref_meander <= z1;
count_in2 <= w1;
 
 
end Behavioral;

---

-----------------------thank u --------------------------------

 

[TrickyDicky]

did you copy and paste from a primitives library?
You cannot use "after" in synthesisable VHDL. you need to use some logical way to delay a signal, like a shift register.

 

[ads-ee]

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sel is
port (s,r :in std_logic;
      qbar : out std_logic);
end sel;
 
architecture Behavioral of sel is
signal q0,q1 : std_logic:= '0';
begin
 
q0 <= s nor q1 after 100 ns   ;-- if  delay not given like this out put not came
q1 <= r nor q0 after 100 ns  ;
qbar <= q1;
 
end Behavioral;

---

I'm not sure what you are tying to do here, are you trying to make an SR latch? Why are you calling the entity sel then?
If you want an SR latch you shouldn't assign both q0 and q1 to 0 one of them should be 1 as having both of them 0 will result in an infinite loop of setting both q1 & q0 to 1 then back to 0 if the s and r are both 0. Until either s or r becomes 1 the q1 & q0 won't become stable and will toggle between states in delta time (when you don't have the after 100 ns). I'm surprised the simulator didn't hit an iteration limit of some sort.