How to add delay elements that are sythesizable to the vhdl code?

[deepthi.reddy.912]

Hi,

I would like to add a delay to a signal like

ctl:sig<=x;
wait for 2.118ns;

But, wait statements are not synthesizable.

I heard that i can add Flipflops or RAMs to make delay synthesizable. But how to add particular delay value like 2.118ns to Flipflop or RAM.

Kindly explain.

 

[BradtheRad]

You can use a counter IC driven by crystal-based oscillator.

You can set up the counter circuit to load any initial value you choose.

Set the counter chip for count down mode.

Then you send a start signal to the counter IC's enable pin.

The crystal oscillator sends precisely spaced pulses. The counter goes down.

When the counter reaches zero, its carry pin will change state. That's your output.

---------- Post added at 13:48 ---------- Previous post was at 13:27 ----------

By the way, if you're talking in resolutions of fractions of a nanosecond that's a tall order.

Light and electronic signals only travel 10 inches per nanosecond.

In that case you could introduce a 2.118ns delay with a carefully measured length of wire. About 25 inches.

It's not inconceivable. I was amazed when I heard about color tv sets sending the chroma signal through a long coil of wire to delay it by a millionth of second so that it would sync with the luminance signal. Or vice versa.

 

[lucbra]

If you want to introduce that kind of delay (order of magnitude a couple of ns), you could think of using a time constraint on that certain path. This way you can define precise delays. buffers (or a double NOT function) with an attribute SYN_KEEP set, can also be used, but the delay will not be precise 2.118ns (as an example)

 

[permute]

time constraints are not precise. they are "less than". eg, if the route ranges from 1ns to 2ns over process/voltage/temperature, then the constraint is met. The path might range from 0.5 to 1ns and also meet the constraint. It isn't accurate or precise if you are trying to get a specific delay. There are precision delay circuits, but they would need to come from your vendor and then you would need to instantiate them and take any other necessary precautions. Usually FPGAs have delay elements for IO purposes, so you might be able to find something of interest there.

But in the majority of cases, delays are specified in terms of cycles or fractions of a cycle. eg, x might be a register that ONLY updates on the falling edge of the clock, while other registers that use it update on the rising edge. or possibly a PLL generates a 90d offset clock. Now 1/4th cycle delays can be realized, as long as the timing constraints can be met.