time constraints are not precise. they are "less than". eg, if the route ranges from 1ns to 2ns over process/voltage/temperature, then the constraint is met. The path might range from 0.5 to 1ns and also meet the constraint. It isn't accurate or precise if you are trying to get a specific delay. There are precision delay circuits, but they would need to come from your vendor and then you would need to instantiate them and take any other necessary precautions. Usually FPGAs have delay elements for IO purposes, so you might be able to find something of interest there.
But in the majority of cases, delays are specified in terms of cycles or fractions of a cycle. eg, x might be a register that ONLY updates on the falling edge of the clock, while other registers that use it update on the rising edge. or possibly a PLL generates a 90d offset clock. Now 1/4th cycle delays can be realized, as long as the timing constraints can be met.