How the synthesier consider CONSTANT and SIGNAL

[khaila]

Supposed we shall add a constant to STD_LOGIC_VECTOR:

A_UNS : in std_logic_vector(3 downto 0);
Y1_UNS : out std_logic_vector(3 downto 0);
Y2_UNS : out std_logic_vector(3 downto 0);
.
.
signal y_uns_std : std_logic_vector(3 downto 0);
constant y_const : std_logic_vector(3 downto 0) := "1111";
.
.
y_uns_std <= "1111";
.
.
Y1_UNS <= A_UNS + y_uns_std ;
Y2_UNS <= A_UNS + y_const ;
.
.

HOW THESIZER will tret Y1_UNS and Y2_UNS ??? Is there any different???

 

[bulx]

yes, a good synthesiser would produce a much smaller circuit than a general prupose 4-bit adder

-b

 

[amitgvlsijune06]

in the first case
1. signal = latch , + = half adder, out = wire
so latch ,adder = wire out

2. input = wire , output = wire, half adder

this will be the difference.its better yu synthesize and check as the signal might be taken as an FF too.
thank you