How the 1.5 bits per stage works? (About Pipelined ADC)

[kennyg]

It seems that 1.5 bits per stage Pipelined ADC architecture is very popular.
Can anyone explain it or give me some information(papers,links,whatever)
about how it works?
I can understand how the 2-bits per stage works.
Using only 2 comparators to decide 3 states(00,01,10) without losing information
confuse me.

How to compensate for the missing 11 state?
Why do we need to shift precision levels 1/4 Vref to the right from the 2 bits per stage architecture and get the residue multified by 2 instead of 4 ?
I have read some pipelined ADC papers,but they didn't explain why
1 bit-overlapping adding can get the correct digital code?

What's the mechanism behind that?

 

[lladnar23]

The standard 1 bit / stage architecture is fine in an ideal world. When you need to tolerate errors and mismatch, etc..., some additional form of redundancy is needed. One common method for improving the error-handling of the pipeline is to simply throw in another decision level so that the quantizer does not overload. (For example, if you tried to make a 1-bit stage (Gain = 2), and had some capacitor mismatch, your decision levels could shift a little bit. This could produce a residue that might be out of the correct range for the subsequent pipeline stage.

 

[mkhafaji]

Dr.wooly handout in stanford university explained it very good. you can see it on his classpage "data converters"

 

[blackbirds]

Dr.wooly handout in stanford university explained it very good. you can see it on his classpage "data converters"

I can't find it,can you tell me where the website is?please!

 

[mince]

You get 1.5 bits at the output with only 1 bit of information. The extra 0.5 bit is redundancy and allows your comparators to not have to be as accurate. If you have a 4 stage pipeline with 1.5 bits per stage, to get your output you would add the bits like:

XX
  XX
    XX
      XX

This would give you a 5 bit output, then you would drop the LSB to get your actual output. For example if your stage outputs were 01, 10, 00, 01 you would have:

  01
    10
      00
        01
----------
   10001

The output is then 1000.

 

[eecs4ever]

Here are two papers with some information.

Does any one have anything else?