jkumar10
Newbie level 3
hi all,
this is related to clock interpretation by tetramax.
i believe tetramax takes all clock definition as asynchronus clock source ( right ? ).
does this hold true for clocks derived internally too ( clock derived at a mux o/p, PLL o/p pin etc?
hence in an SDC definition false paths from clock to clock is unnecessary to define as tetramax will not generate any patterns for those.
though we are still facing coverage drop when read an SDC with clock to clock false paths definition
& satisfactory coverage improvement without clock to clock false paths definition.
Is my above understanding correct ?
also does the tetramax runtime increases after reading a SDC ?
regards,
jkumar
this is related to clock interpretation by tetramax.
i believe tetramax takes all clock definition as asynchronus clock source ( right ? ).
does this hold true for clocks derived internally too ( clock derived at a mux o/p, PLL o/p pin etc?
hence in an SDC definition false paths from clock to clock is unnecessary to define as tetramax will not generate any patterns for those.
though we are still facing coverage drop when read an SDC with clock to clock false paths definition
& satisfactory coverage improvement without clock to clock false paths definition.
Is my above understanding correct ?
also does the tetramax runtime increases after reading a SDC ?
regards,
jkumar