Dear,
You misunderstood my question. Actually I have a flip flop of standard cell library. Now its setup time is fixed. Recently in one interview I was asked how can we reduce that setup time. And the answer was, if we connect the flip flops in cascade we can reduce the setup time with out touching the combinational logic. But I am confused how can it happen ? Say we have two flip flop having 1ns setup time and in between those flops we have combinational logic having 150ns propagation delay. now clock is running such that setup time violation occuring. So without touching the combinational logic and clock, how can we to reduce the setup time of the second flipflop to 0.5ns ?
Thanks