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Normally when we see a very long data path betn flops, the setup tends to violate. One of teh ways to fix it is to break the data path into two by inserting a flop in between. Thus, it appears as a cascade!!!
Dear,
You misunderstood my question. Actually I have a flip flop of standard cell library. Now its setup time is fixed. Recently in one interview I was asked how can we reduce that setup time. And the answer was, if we connect the flip flops in cascade we can reduce the setup time with out touching the combinational logic. But I am confused how can it happen ? Say we have two flip flop having 1ns setup time and in between those flops we have combinational logic having 150ns propagation delay. now clock is running such that setup time violation occuring. So without touching the combinational logic and clock, how can we to reduce the setup time of the second flipflop to 0.5ns ?
Thanks
hi sunil
I read ur question.
we can not change the minimum setup time req of 2nd ff.
I think setup time violation for 2nd FF can be avoided by putting a buffer in clock path of 2nd FF.So that clk edge will come late(buffer delay) at 2nd FF,where as data is present at usual time.
I'm not getting the concept of cascading of FF.
thanks, eager to hear from u.
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