i have 2 designs of a logic(combinational) (for example 6T XOR and 16T XOR)
i am fabricating that in a chip. two identical 16T XOR and one 6T XOR. those are kept very near to each other in the layout. obviously the first two layouts are identical. same number of transistor, same W/L for corresponding transistors, and same number of interconnects. everything is different for the third one. in the normal PVT corner all of them (two identical design and the different one) give same delay. in a different pvt condition how will they behave? can i expect same delay or will they give different delays?
thank you for the fast response Fahmy and Prashanthanilm.
let me clear once again.
i have 3 designs, two identical and one different . in the new pvt condition the delay will be different from the previous pvt condition. but in the new pvt condition what will be the delay of the three designs? will that be same for everything or for each designs will it be different. hope you get my question this time
two identical designs have same delay (same design i am duplicating)
the third one (which is different) is designed to get the same delay by changing the W/L ratio
at a different pvt condition
the delay will be different from the first pvt condition
but my question is
will the three design will give same delay (which is different from the first pvt condition)
or
the identical two will give same delay and third one will give a different delay
or
all the three will give different delay