how pvt variations affect delay

[midhs]

i have 2 designs of a logic(combinational) (for example 6T XOR and 16T XOR)
i am fabricating that in a chip. two identical 16T XOR and one 6T XOR. those are kept very near to each other in the layout. obviously the first two layouts are identical. same number of transistor, same W/L for corresponding transistors, and same number of interconnects. everything is different for the third one. in the normal PVT corner all of them (two identical design and the different one) give same delay. in a different pvt condition how will they behave? can i expect same delay or will they give different delays?

 

[Fahmy]

It is very very unlikely to happen to get the same delay from two designs across PVT

 

[Prashanthanilm]

PVT changes the delay. as Fahmy told it is not expected to get the same delay from two design across PVT.

Run simulations on the design individually, Hope it clear the doubt.

 

[midhs]

thank you for the fast response Fahmy and Prashanthanilm.
let me clear once again.
i have 3 designs, two identical and one different . in the new pvt condition the delay will be different from the previous pvt condition. but in the new pvt condition what will be the delay of the three designs? will that be same for everything or for each designs will it be different. hope you get my question this time

 

[Prashanthanilm]

If the design is different , how can the result be same with same PVT.

Considering , PVT changes the op point slightly of each transistors present.

Also, it depends on how the two architecture. If they are electrically similar then the variation wrt to PVT will be less.

Did I get the question right?. Let me know if any issues.

 

[midhs]

at normal pvt conditions

two identical designs have same delay (same design i am duplicating)
the third one (which is different) is designed to get the same delay by changing the W/L ratio


at a different pvt condition

the delay will be different from the first pvt condition

but my question is

will the three design will give same delay (which is different from the first pvt condition)
or
the identical two will give same delay and third one will give a different delay
or
all the three will give different delay

 

[Prashanthanilm]

Ok.
At Normal PVT

All 3 design will give same delays.

At Different PVT,

Since the 2 Identical design have same W/L-> The delay will be the same.

But for the 3rd design , since the architecture is different. The W/L ratio is different compared to the first two design.

`> Change in W/L will change resistance and also due to PVT change there is change in Vth. So, the 3rd design will have diff delay.


"the identical two will give same delay and third one will give a different delay"

Hope it is clear now and helps too

 

[midhs]

thank you very much Mr Prashanthanilm.

can i have any theoretical proof or any article, journal or something which can be used as a reference ?

hope you will help me

 

[Prashanthanilm]

This is very good article. (May not be the perfect answer for your question).

But very good details about PVT you can find here.

https://asic-soc.blogspot.in/2008/03/process-variations-and-static-timing.html

Thank you,
Prashanth