How often would " alpha particle" affect logic in chips? any idea?

[layowblue]

In order to protect data from error caused by alpha particles, data-integrity protection mechanism is usually employed in digital chip design. One normal way is to put parity value along with data.
But, does anyone know:
1) how likely the "alpha particle" phenomenon happens?
2) Is there a formula to calculate the possibility?
3) What are the contributing factors that results in alpha particle(or those kind of)-related error inside the chip?

Thanks a lot!

 

[dick_freebird]

1) depends on location and on composition of packaging
materials.

2) When you know your environment's alpha flux, your
circuit's sensitive cross section will give you the error
rate.

3) Simple charge per bit, which industry strives to minimize.
Some topologies have more resliience than others, design
choices like device size and bias level and error-mitigating
topologies (or, designing in things like state machines with
lockup states that never get accessed normally, but could)

Look to memory design conferences and IEEE NSREC for
enough on this to choke you.

 

[layowblue]

Thanks a lot dick_freebird.
Also, could you give me an example? Like in normal city environment, for a given scale of chips, what is the average absolute value of the alpha particle error happens? Is it is scale of say once every 1 million years?

Thanks again

 

[dick_freebird]

At sea level this comes down to the packaging and device
construction, cosmic alphas rarely if ever reach the ground.
But neutrons do, and boron-10 (a low-percentage isotope)
will convert a captured neutron into an alpha particle in-situ.
So you see folks like memory companies sourcing their borane
isotopically pure, just to get rid of this almost-never times
almost-never probability. Because when you're sitting on
gigabytes of DRAM, suddenly "hardly ever, per bit" becomes
not so comforting.

Other packaging materials can also contain low level alpha
emitters, if you didn't say not to.

Now, locations like on-orbit and aviation and very high
elevation will have some environmental alphas. These, you
chat up a NASA "space weather" science type or dig for
the classical mission fluence charts. It's very variable
between orbits and over time; usually you assume the worst.
None of this pertains to sea level under concrete, really.
Although I reckon maybe somebody has worked it out.

You might find more commercial-world info searching for
things like "DRAM soft error rate". For me, this doesn't matter
because my job is to make circuits that don't upset even
with heavy ions. But that is far from the norm, and no DRAM
design is going to want the penalties associated with such
bullet-proofing. They do the easy things, and maybe go as
far as trying to make sure no two bits in a word are adjacent
so as to eliminate non-correctable multi-bit upsets. But they
are not going to make the DRAM array cells one iota bigger
than it takes to guarantee retention time / refresh rate.

 

[rca]

by alpha particul, did you mean the x-ray solar radiation?

IBM made ana analyzis an estimate than 1bit overs 100Mbit of RAM will change every month due to that. (article available on internet or wikipedia page)