How many leakage current is reasonable for a chip (10V) ?

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Areky_qin

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chip leakage?

Hi, someone could tell me how many leakage current is reasonable for a chip, when power supply is 10v? eg, pmos must have leakage from n-well substrate to p-implant, nmos have leakage from n-implant to p-well, most of the full chip leakage is led via those two path. Thanks
 

Re: chip leakage?

The leakage current depends on the transistor behavior, so you should check with your process information.
 

chip leakage?

It depends on what kind of process. For common CMOS process >0.25um, the transistor leakage is as low as nA order. Therefore, most of leakage come from careless design. For CMOS process <0.18um, the transistor leakage play the main part of the chip leakage
 

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