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How many about decouple capacitance?

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Advanced Member level 4
Jul 15, 2002
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decouple capacitance

I have to design a evaluation board by using BGA package FPGA. pin count to 676. how to arrange the decouple capacitance? and how many is enough. coz BGA package have high desity of routing :( , and both top and bottom layer have many VIA :? . and where to place all decouple capacitance? :?: :?: :?:

decoupling capacitor bga

A highly successful company which has its designs work the first time every time has a design rule that there is one bypass on each power pin of all ICs. These are on the back side of the pc card right up agains the via that supplies the power to each pin. The size of the capacitors are set by the frequency of the signals. They try to have at least one 0.1 uF per IC minimum and on ones with multiple power pins they alternate 0.1 uF and 10 nF.

decouple capacitor

for QFP, I have add capacitors to each power pin on one chip at the back of the board. but this BGA package have 26 X 26 array. so there must be lots of via, no other place for capacitors. i find some evalution board. they add some, but not for each power pin. is there any design rule for decouple capacitor? how many power pin should share one capacitor?

power supply decoupling capacitor size


I have used this solution on several board with BGA package

1) Power plane
Each supply must have its own power plane.
For the internal supply its enough that its cover the BGA and the decouple capacitors
For IO supply its must also include all the area were the IO signals are.
The power pins shall be connected directly to the power plane.

2) Decouple capacitor
The general rule is one for each power pin.
The typical value is 0.1 uf or lower for more high speed signal
You have to look on the resonance frequency so the capacitor is working at your high speed signal.

On the BGA is not working with one capacitor for every power pin but instead you put as many as practical around the BGA, and inside (secondary side) if not a filled one.
You should also do a check with a good oscilloscope.

The version with multiple capacitor with different values in parallel I don’t recommend, because
the resonance frequency its so manufacture/batch depended.

Use only X7R or NP0 capacitors.
The capacitors shall be connected directly to the power plane.

3) Bulk capacitor
Depending how much current the BGA consumes and how near your power supply are,
you may need some bulk capacitors.
Use low ESR tantal capacitor

For more information you can read Dr. Howard Johnson articles at his excellent site

Micron has also a technical note: Bypass Capacitor Selection,


bga capacitance

oh thanks, jzo. i will try it. :) :)

decouple pins

Here is another very good technical note:
**broken link removed**

0.1 uf at each power pin

Thanks, it is just Xilinx V2 FPGA. it is the first time for me to design such chip. :)

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