Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How insert clock gating in module level?

Status
Not open for further replies.

horzonbluz

Full Member level 4
Joined
May 1, 2002
Messages
208
Helped
11
Reputation
22
Reaction score
9
Trophy points
1,298
Activity points
1,530
In power compiler 2003.12 version, it support a new command "insert_clcok_gating -module_level", but how to insure that it insert this kind of clock gating using TEST_MODE signal as its test enable signal?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top