prafiee
Newbie level 5
optimized space in vhdl
Dear every body
I want to know how I can optimize space used of cpld or fpga based on vhdl code to reduce consumed space. I think most of used space for my code (chich is unnormal) is due to presence of one 24 bits comparator:
if (ASig < 8e6) then
.......
end if;
Dear every body
I want to know how I can optimize space used of cpld or fpga based on vhdl code to reduce consumed space. I think most of used space for my code (chich is unnormal) is due to presence of one 24 bits comparator:
if (ASig < 8e6) then
.......
end if;