how generate xilinx coregen without clk

[rajavel.rv]

Hiiii... am need a combination memory core for without clk, how can generate that in xilinx core..

 

[barry]

I don't know what a "combination memory core" is, but I believe all the Xilinx memory blocks are synchronous(they need a clock). If you really want non-synchronous memory, and I don't know why you would, you can just instantiate it in your code-I don't think you will be able to use coregen.

 

[rca]

how large is your memory, you could used flop instead mems?

 

[rajavel.rv]

my memory size was 256 bytes, i have generated that in distributed without clk, but i need that in block ram, how can i generated that... it possible or not...

 

[FvM]

You're essentially asking about hardware features of the involved FPGA rather than IP cores. By nature of the block RAM implementation in recent FPGA, the access is synchronous and requires a clock. You'll find details in the device datasheet and specific block RAM user guides.

 

[rajavel.rv]

Thanks, we are taken a rom_model in verilog from device datasheet to design a rom;
reg [7:0] rom_mem [255:0];
my doubt was how this style taken as a block rom or distributed rom in inside of fpga; how can i check this one;

 

[barry]

You can look at your report and see how the tool allocated your ROM, whether it used distributed RAM or Block RAM

 

[rajavel.rv]

Single port block rom in combinational

Hi everybody, am need a single port block ram in combination logic; how can am design that logic in rtl using verilog hdl;
pls help me;

Thanks & Regards;
Rajavel

 

[FvM]

Re: Single port block rom in combinational

I believe you know pretty well that combinational block RAM isn't available with recent FPGA, e.g. Spartan, as discussed in your previous thread https://www.edaboard.com/threads/309459/

The answer doesn't change if you shift the question to Verilog coding, beacuse it's still a FPGA hardware problem.

What you are exactly trying to achieve now?

 

[rajavel.rv]

They are given in device data sheet for

https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/xst_v6s6.pdf



vROM Modeled With Initial Block Verilog Coding Example

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
reg [15:0] rom [15:0];
initial begin
rom[0] = 16'b0011111100000010;
rom[1] = 16'b0000000100001001;
rom[2] = 16'b0001000000111000;
rom[3] = 16'b0000000000000000;
rom[4] = 16'b1100001010011000;
rom[5] = 16'b0000000000000000;
rom[6] = 16'b0000000110000000;
rom[7] = 16'b0111111111110000;
rom[8] = 16'b0010000010001001;
rom[9] = 16'b0101010101011000;
rom[10] = 16'b1111111010101010;
rom[11] = 16'b0000000000000000;
rom[12] = 16'b1110000000001000;
rom[13] = 16'b0000000110001010;
rom[14] = 16'b0110011100010000;
rom[15] = 16'b0000100010000000;
end

---

but is created warning

WARNING:Xst:2999 - Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

how can i solve this;

 

[FvM]

Signal 'mem', unconnected

How did you connect the ROM? There should be also a statement like below in your code.

do <= ROM[addr];

 

[rajavel.rv]

How did you connect the ROM? There should be also a statement like below in your code.

do <= ROM[addr];

yes, am also put that statement in my code; but its was not problem; where am put that statement its inside of assign statement or always statement; am try this in both but the warning was came;

---

Code Verilog - [expand]
1
2
3
4
5
6
reg [15:0] rom [15:0];
initial begin
rom[0] = 16'b0011111100000010;
rom[1] = 16'b0000000100001001;
rom[2] = 16'b0001000000111000;
end

---

am assigning the value rom[0] = 16'b0011111100000010; inside of initial block means the error came but at the same time am assigning that inside of always block means its did not come;;
but the always block was generated at LUT; am need a block ram; that is a problem;

 

[FvM]

May be guess, this isn't a clock edge sensitive always block?