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how does the tool 'synplify' synthesize sysnopsys DW02_mac?

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quan228228

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Re: how does the tool 'synplify' synthesize sysnopsys DW02_m

In my 8051, there is a synopsys DW02_mac block. The simulation is right. But
When i run fpga, find that the mac can't work.

The mac funciotn is a*b+c;

for example,
a = 16'h0001, b = 16'hffff, c = 32'h0000_0000;

the fpga result is 32'h0000_00001;
the simulation result is 32'hffff_ffff;

Is the fault related with fpga synthesis or code? Or is there corresponding lib for DW02_mac?

Please help me. Thanks very much.
Following is DW02_mac.v;

module DW02_mac
(A, B, C, TC, MAC);

parameter A_width=8;
parameter B_width=8;

// port list declaration in order
input [ A_width- 1: 0] A;
input [ B_width- 1: 0] B;
input [ A_width+B_width- 1: 0] C;
input TC;
output [ A_width+B_width- 1: 0] MAC; reg [ A_width+B_width- 1: 0] MAC;

function [ A_width+B_width- 1: 0] signed_mult;
input [ A_width- 1: 0] A;
input [ B_width- 1: 0] B;
reg [ A_width- 1: 0] a1;
reg [ B_width- 1: 0] b1;
reg [ A_width+B_width- 1: 0] c1;
begin
// synopsys synthesis_off
if ( (A[A_width-1] === 1'bx || B[B_width-1] === 1'bx) ) begin
signed_mult = {A_width+B_width{1'bx}};
end else
// synopsys synthesis_on
begin
if (A[A_width-1] === 1'b1)
a1 = -A;
else
a1 = A;
if (B[B_width-1] === 1'b1)
b1 = -B;
else
b1 = B;
c1 = a1*b1;
if (A[A_width-1] !== B[B_width-1])
signed_mult = -c1;
else
signed_mult = c1;
end
end
endfunction

always begin
if ( TC === 1'b1 ) begin // signed multiplication
MAC <= signed_mult(A,B)+C;
end else begin
MAC <= A*B+C;
end // if
@(TC or A or B or C);
end // process

endmodule

Added after 1 hours 44 minutes:


i wonder if the function is sythesisable.


David
 

kelvin_sg

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I doubt whether Synopsys allow user to synthesize their designware modules in other synthesizers.

The Verilog modules you get are most likely intended for simulation only.

HTH
 

quan228228

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Re: how does the tool 'synplify' synthesize sysnopsys DW02_m

yeh, i also have this doubt. Do u know, is the statement 'function' synthesisable or not.


If not, how to map DW block into FPGA ?

Thanks!


David
 

ls000rhb

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// synopsys synthesis_off
if ( (A[A_width-1] === 1'bx || B[B_width-1] === 1'bx) ) begin
signed_mult = {A_width+B_width{1'bx}};
end else
// synopsys synthesis_on
implys it is a code for simulation
Why not replace this DW with your own code?
 

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