How does the simulator overcome negative timing checks?

[sudha]

negative timing checks

During timing simulation many a times we do face issues with negative timings checks. when we have negative timing checks, how does the simulator (modelsim) overcome those. Am well aware there are options to make the -ve values set to zero and continue the simulation, but how does the simulator work if we say negative timings must be included during simulation. can anyone pls help me on this.

 

[brmadhukar]

Re: negative timing checks

Do you mean negative hold times. It is not a problem for design. Can you provide more information
BRM

 

[sudha]

Re: negative timing checks

by saying negative timing checks i mean negative setup and hold times of signals, these timing details are available in sdf file. when the simulator(modelsim) tries to back annotate, whts happening to these timings.
for example... if i take a dff from standard tsmc18 library, which consists of setup, hold... timings. now if i make setup time negative and simulate... whts are the happenings in the simulator.
tnx

 

[brmadhukar]

Re: negative timing checks

Hi,
If you input -ve timings the modelsim forces it '0'.
BRM

 

[skynet]

Re: negative timing checks

if you have negative setup time, and perform simulation, your will get warming message saying that you have violation