How does a STA engineer uses a liberty file

[satishgra]

Hi,

I am a professional characterization engineer having good knowledge about liberty file generation. But, I wonder how exactly the final .lib file is used by the backend guys. We have quite a few parameters like cell rise/fall, rise/fall propagation, setup/hold.....etc

My questions are :

• 
  Why do we need both propagation & transition delays....How does one use them in real time STA flow

• 
  what are the various checks that one does during STA using the .lib file

Any link would be greatly appreciated....



Regards,
Satish Grandhi
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[rca]

Quite strange question, I believe you never done a synthesis.
In a suite of logic element, the tool will used the transition, to determine the slowest path, and with the RC back annotation, it will determine the transition seen by the cell input and calculate the transition in cell output. The STA will used the liberty, to check the trans, cap, fanout, setup, hold, max freq.

 

[satishgra]

I am looking for a detailed flow or a document in this regard

 

[rangk]

STA is a timing check.. basically used to check for setup,hold violations,delays etc..
In a .lib file, we have only the delays or the rise time-fall time for standard cells of that particular Library. Now during synthesis, these standard cells will be used to make the logic circuit to replicate the functionality.
At the top-level, when you need to know what exactly is the delay, for ex, all that you would do is try and find what is the slew of that input pin and what is the corresponding output load seen by each of the std cells and get the delays by referring to the .lib file.. now these delays will be added to find the overall delay in that data path.

Now the same thing will be used for ckts involving sequential logic.
These delays will again be used to find out the data arrival time (Time taken by the data to arrive at the input pin of a flop) this is compared with the data required time (Setup time of the flop, taken from the .lib) now the slack time is calculated by subtracting required time from arrival time. If this is -Ve then u have a setup violation at that flop. hold voilations are also found out in the same manner.

Hope this solves ur doubts.

 

[dftrtl]

For your IP level synthesis and STA we use the .lib of ASIC cells.

 

[ivlsi]

rca, you wrote:

with the RC back annotation, it will determine the transition seen by the cell input and calculate the transition in cell output

Could you please explain how does it translate an input transition to output transition? As far as I know, using RC values from back-annotation, the tool calculates delays on the net connected to the cell's output(s). Does it do it without WLM? So, where does it take the corresponded transition values from? I believe that for the same RC values the different cells will receive different transition values... How input transitions are taken into consideration?

 

[ivlsi]

In a .lib file, we have only the delays or the rise time-fall time for standard cells of that particular Library.

Propagation delays appear in *.lib files as well as transition delays?
Are propagation delays also affected by fanout# (RC values) as well as transition delays?

 

[mail4idle2]

Propagation delay is nothing but the transistion reaching 50% of its logic Value.

 

[ivlsi]

transistion reaching 50% of its logic Value

I don't understand this... reaching 50% of its logic Value? What do you mean?