Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How does a STA engineer uses a liberty file

Status
Not open for further replies.

satishgra

Member level 3
Joined
Mar 29, 2008
Messages
59
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
Bangalore
Activity points
1,717
Hi,

I am a professional characterization engineer having good knowledge about liberty file generation. But, I wonder how exactly the final .lib file is used by the backend guys. We have quite a few parameters like cell rise/fall, rise/fall propagation, setup/hold.....etc

My questions are :

  • Why do we need both propagation & transition delays....How does one use them in real time STA flow


  • what are the various checks that one does during STA using the .lib file


Any link would be greatly appreciated....



Regards,
Satish Grandhi
NO SIGNATURE LINKS ALLOWED
 

rca

Advanced Member level 4
Joined
May 20, 2010
Messages
1,485
Helped
354
Reputation
708
Reaction score
326
Trophy points
1,363
Location
Marin
Activity points
8,522
Quite strange question, I believe you never done a synthesis.
In a suite of logic element, the tool will used the transition, to determine the slowest path, and with the RC back annotation, it will determine the transition seen by the cell input and calculate the transition in cell output. The STA will used the liberty, to check the trans, cap, fanout, setup, hold, max freq.
 

satishgra

Member level 3
Joined
Mar 29, 2008
Messages
59
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
Bangalore
Activity points
1,717
I am looking for a detailed flow or a document in this regard
 

rangk

Newbie level 4
Joined
Oct 11, 2010
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,318
STA is a timing check.. basically used to check for setup,hold violations,delays etc..
In a .lib file, we have only the delays or the rise time-fall time for standard cells of that particular Library. Now during synthesis, these standard cells will be used to make the logic circuit to replicate the functionality.
At the top-level, when you need to know what exactly is the delay, for ex, all that you would do is try and find what is the slew of that input pin and what is the corresponding output load seen by each of the std cells and get the delays by referring to the .lib file.. now these delays will be added to find the overall delay in that data path.

Now the same thing will be used for ckts involving sequential logic.
These delays will again be used to find out the data arrival time (Time taken by the data to arrive at the input pin of a flop) this is compared with the data required time (Setup time of the flop, taken from the .lib) now the slack time is calculated by subtracting required time from arrival time. If this is -Ve then u have a setup violation at that flop. hold voilations are also found out in the same manner.

Hope this solves ur doubts.
 

dftrtl

Banned
Joined
Feb 1, 2011
Messages
349
Helped
76
Reputation
152
Reaction score
73
Trophy points
1,308
Location
Bangalore
Activity points
0
For your IP level synthesis and STA we use the .lib of ASIC cells.
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
879
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,806
rca, you wrote:
with the RC back annotation, it will determine the transition seen by the cell input and calculate the transition in cell output
Could you please explain how does it translate an input transition to output transition? As far as I know, using RC values from back-annotation, the tool calculates delays on the net connected to the cell's output(s). Does it do it without WLM? So, where does it take the corresponded transition values from? I believe that for the same RC values the different cells will receive different transition values... How input transitions are taken into consideration?
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
879
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,806
In a .lib file, we have only the delays or the rise time-fall time for standard cells of that particular Library.
Propagation delays appear in *.lib files as well as transition delays?
Are propagation delays also affected by fanout# (RC values) as well as transition delays?
 
Last edited:

mail4idle2

Full Member level 4
Joined
Oct 20, 2012
Messages
200
Helped
20
Reputation
40
Reaction score
19
Trophy points
1,298
Activity points
2,173
Propagation delay is nothing but the transistion reaching 50% of its logic Value.
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
879
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,806
transistion reaching 50% of its logic Value
I don't understand this... reaching 50% of its logic Value? What do you mean?
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top