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zeese said:Will this code is synthesized into latch?
always @ (posedge clk)
begin
if (!rst)
out <= 0;
else
begin
if (enable)
out <= din;
end
end
In the above code, only if statement exist, but no else. But there a
reset condition. So, will this become latch ?
ddtiantian said:Latch are used for high performance designs. There is a good paper talks about computing/verifying the cycle time for designs with many latches, given the setup/hold and delay of combinational logic.
"Verifying Clock Schedules," Thomas G. Szymanski, Narendra Shenoy, ICCAD 1992, pp. 124-131