How do you synthesize a latch?

[no_mad]

latch synthesis

Hi all,

How do you synthesize a latch?

Thanx in advance
no_mad

 

[eda_wiz]

Latch synthesis

//RTL code for latch.
always@(EN or b) begin
if(EN) a = b;
end

 

[no_mad]

Latch synthesis

Thanx, I already know how to code a latch.

Actually, my question is how do u do STA for a latch in Design Compiler.

Sorry, my question is too simple.

 

[zeese]

Re: Latch synthesis

Will this code is synthesized into latch?

always @ (posedge clk)
begin
if (!rst)
out <= 0;

else
begin
if (enable)
out <= din;
end
end

In the above code, only if statement exist, but no else. But there a
reset condition. So, will this become latch ?

 

[no_mad]

Latch synthesis

hi zeese,

This code is a D-latch with sync active low reset signal.

 

[eda_wiz]

Re: Latch synthesis

Will this code is synthesized into latch?

always @ (posedge clk)
begin
if (!rst)
out <= 0;

else
begin
if (enable)
out <= din;
end
end

In the above code, only if statement exist, but no else. But there a
reset condition. So, will this become latch ?

this will be a d-flop with a mux connected to input .. one i/p of mux is the d-flop out and other i/p is din.

 

[visualart]

Latch synthesis

WHY Do you need the latch in the design?It is not teatable but for the LSSD of the IBM.
A good desgin don't include the latch

 

[Thinkie]

Re: Latch synthesis

My suggestion is to avoid latched if you can.

They will cause timing problems and will harm the testability of your design

 

[srik_naidu]

Latch synthesis

hi,

in case of vhdl:-
if en='1' then
q<=d;
end if;

with regards,
srik.

 

[ddtiantian]

Latch synthesis

Latch are used for high performance designs. There is a good paper talks about computing/verifying the cycle time for designs with many latches, given the setup/hold and delay of combinational logic.
"Verifying Clock Schedules," Thomas G. Szymanski, Narendra Shenoy, ICCAD 1992, pp. 124-131

 

[dBUGGER]

Re: Latch synthesis

Latch are used for high performance designs. There is a good paper talks about computing/verifying the cycle time for designs with many latches, given the setup/hold and delay of combinational logic.
"Verifying Clock Schedules," Thomas G. Szymanski, Narendra Shenoy, ICCAD 1992, pp. 124-131

Hi ddtiantian,
I am not able to locate this paper. Can you please upload this on this site. Thank you.

Best Regards,

 

[eeeraghu]

Re: Latch synthesis

Latch Basics

 

[ddtiantian]

Re: Latch synthesis

Here is the "Verifying Clock Schedules" paper.