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If you go through the datasheet for the clock IC your implementing,you might find the routing topology there somewhere.
It always better to route clk signal between ground planes,if you find it difficult to accomplish between the planes then route it in the component side with ground guarding/ground pour around.
First thing you need to figure it out about the aggressor near the clock signal and ensure it is away from it,then the length of clock signal is also crucial.google with proper string,you will get tons of articles related to it.
It always better to route clk signal between ground planes,if you find it difficult to accomplish between the planes then route it in the component side with ground guarding/ground pour around.
Here two explanations about why CLOCK should be routed in the C.S.:
Route the clock trace on the microstrip (preferably top layer) to
minimize the use of vias and delays, since air is the dielectric material.
Air has the lowest dielectric constant (Er = 1).
Route the clock in the C.S. Avoid using vias in the clock transmission line, since vias can contribute impedance change and reflection.
The upon two facts are correct, so why there another opinions call to route the clock between two GND planes???
Like almost everything in electronics, there are trade-offs that have to be made. A clock signal uses the rising and/or falling pulse edges for timing the rest of the circuit. The pulse edges contain all of the desired information, the pulse itself has no useful data. As a result, the PCB layout should be done in such a way so as to minimize distortion of the pulse edges. At the same time, those fast pulse edges are rich in harmonics that can couple into other circuitry on the board or radiate from the board, so you want to isolate and shield the clock from other vulnerable circuitry as much as possible.
If you place the clock on the outside surface of a PCB, you accomplish one of the above goals - you reduce the amount of distortion to the signal edges. Sandwiching the clock between ground planes on an inner layer increases the capacitance and loss per unit length along the trace. Increased capacitance translates into increased delay, resulting from increased loss of the higher frequency components of the signal edge. Increased loss results in lower edge voltages to trigger or drive other parts of the circuit.
On the other hand, sandwiching the clock between ground layers reduces the likelihood of radiating from the PCB, and makes it easier to decouple the clock from other potential victim traces elsewhere on the board. That's a benefit of suppressing the higher frequency components of the signal edge.
You can accomplish both goals in layout by simply being aware of what is happening. Lay out the fast clocks on the surface of the board, but keep them away from other traces (i.e. don't route other traces in parallel with them, keep them separated from other traces by at least 3X the width of the clock trace to keep the mutual coupling below about 30db, make sure there's an unbroken continuous return path on a plane layer directly below the clock trace to minimize the signal loop, match impedance of the trace to sink and source to transfer maximum energy from source to sink, and where possible shield the board from external victim circuits).
If you must place the clock on an internal layer, calculate the skew and threshold changes that will result from the increased capacitance. Distribute the clock signal in such a way to equalize the skew across all the clock sinks and guarantee that you will be well above any clock receiver threshold requirements. As in the surface routed case, minimize parallel tracks, keep tracks separated to reduce coupling to a minimum, and ensure that there is an uninterupted return path available to keep the signal loop minimized.
Engineering is always an exercise in compromise - there's never one answer that is perfect.
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